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MC92602RM/D 3/2003 REV 0
MC92602 Quad 1.25 Gbaud Reduced Interface SERDES Reference Manual
Devices Supported: MC92602ZTA
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003
Introduction
Transmitter Receiver Rate Adaption of IEEE Standard 802.3 Packet Streams System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
1 2 3 4 5 6 7 8 A B GLO IND
1 1 2 3 4 5 6 7 8 A B GLO IND
Introduction
Transmitter Receiver Rate Adaption of IEEE Standard 802.3 Packet Streams System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
Contents
Paragraph Section Number Title About This Book Audience .............................................................................................................. xiii Organization......................................................................................................... xiii Suggested Reading............................................................................................... xiv General Information..................................................................................... xiv Related Documentation ............................................................................... xiv Conventions ...........................................................................................................xv Signals....................................................................................................................xv Chapter 1 Introduction 1.1 1.2 1.3 1.4 1.5 Overview.............................................................................................................. 1-1 Features ................................................................................................................ 1-2 Block Diagram ..................................................................................................... 1-3 References............................................................................................................ 1-5 Revision History .................................................................................................. 1-5 Chapter 2 Transmitter 2.1 2.2 2.3 2.3.1 2.3.1.1 2.3.1.2 2.3.1.3 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 Transmitter Block Diagram ................................................................................. 2-1 Transmitter Interface Signals ............................................................................... 2-2 Functional Description......................................................................................... 2-4 Transmit Data Input Register Operation.......................................................... 2-4 Transmitting Uncoded Data......................................................................... 2-5 Transmitting Coded Data............................................................................. 2-5 Transmit Interface Clock Configuration ...................................................... 2-6 8B/10B Encoder Operation.............................................................................. 2-6 Transmit Driver Operation............................................................................... 2-6 Transceiver Disable.......................................................................................... 2-7 Loop-Back Test Mode...................................................................................... 2-7 Repeater Mode................................................................................................. 2-8 Page Number
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Contents
Paragraph Number Title Chapter 3 Receiver 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.3.1 3.3.3.2 3.3.4 3.3.4.1 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.7 3.3.7.1 3.3.7.2 3.3.8 3.3.9 Receiver Block Diagram...................................................................................... 3-1 Receiver Interface Signals.................................................................................... 3-2 Functional Description......................................................................................... 3-4 Input Amplifier................................................................................................. 3-5 Transition Tracking Loop and Data Recovery ................................................. 3-5 Byte Alignment ................................................................................................ 3-6 Byte-Aligned................................................................................................ 3-6 Non-Aligned ................................................................................................ 3-7 Word Synchronization ..................................................................................... 3-7 Recommended Settings for Word Synchronization ..................................... 3-8 8B/10B Decoder .............................................................................................. 3-9 Receiver Interface ............................................................................................ 3-9 Byte Interface............................................................................................. 3-10 Ten-Bit Interface ........................................................................................ 3-10 Receiver Interface Error Codes.................................................................. 3-10 Receiver Interface Clock Timing Modes ....................................................... 3-12 Recovered Clock Timing Mode ................................................................. 3-12 Reference Clock Timing Mode.................................................................. 3-13 Half-Speed Mode........................................................................................... 3-14 Repeater Mode............................................................................................... 3-14 Chapter 4 Rate Adaption of Packet Data Streams 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 Rate Adaption Method ......................................................................................... 4-2 Configuration Context...................................................................................... 4-2 Idle Context...................................................................................................... 4-3 Data Context .................................................................................................... 4-3 Error Handling ..................................................................................................... 4-4 Special Considerations......................................................................................... 4-5 Chapter 5 System Design Considerations 5.1 5.2 5.3 5.4 5.5
vi
Page Number
Reference Clock Configuration............................................................................ 5-1 Startup .................................................................................................................. 5-2 Standby Mode ...................................................................................................... 5-2 Configuration and Control Signals....................................................................... 5-2 Power Supply Requirements................................................................................ 5-3
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Contents
Paragraph Number 5.6 5.7 5.8 Title Page Number
Phase Locked Loop (PLL) Power Supply Filtering............................................. 5-4 Power Supply Decoupling Recommendations..................................................... 5-4 HSTL Reference Voltage Recommendation ........................................................ 5-5 Chapter 6 Test Features
6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 6.2.1 6.2.2 6.3
IEEE Std. 1149.1 Implementation ....................................................................... 6-1 Test Access Port (TAP) Interface Signals ........................................................ 6-1 Instruction Register.......................................................................................... 6-2 Instructions....................................................................................................... 6-2 Boundary-Scan Register .................................................................................. 6-3 Device Identification Register (0x0281601D) ................................................. 6-3 Performance ..................................................................................................... 6-3 System Accessible Test Modes ............................................................................ 6-3 Loop Back System Test ................................................................................... 6-3 BIST Sequence System Test Mode.................................................................. 6-4 Loop-Back BIST Sequence System Test Mode................................................... 6-6 Chapter 7 Electrical Specifications and Characteristics
7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5
General Characteristics ........................................................................................ 7-1 General Parameters .......................................................................................... 7-1 Absolute Maximum Rating.............................................................................. 7-2 Recommended Operating Conditions.............................................................. 7-2 DC Electrical Specifications ................................................................................ 7-3 AC Electrical Characteristics ............................................................................... 7-4 Parallel Port Interface Timing.......................................................................... 7-4 Reference Clock Timing ................................................................................. 7-6 Receiver Recovered Clock Timing .................................................................. 7-7 Serial Data Link Timing .................................................................................. 7-8 JTAG Test Port Timing .................................................................................... 7-9 Chapter 8 Package Description
8.1 8.2 8.3 8.4
196 MAPBGA Package Parameter Summary ..................................................... 8-1 Nomenclature and Dimensions of the 196 MAPBGA Package .......................... 8-1 Package Thermal Characteristics ......................................................................... 8-5 MC92602 Chip Pinout Listing............................................................................. 8-5
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Contents
Appendix A Ordering Information Appendix B 8B/10B Coding Scheme B.1 B.1.1 B.1.2 B.1.3 B.2 Overview..............................................................................................................B-1 Naming Transmission Characters ....................................................................B-2 Encoding ..........................................................................................................B-2 Calculating Running Disparity ........................................................................B-3 Data Tables...........................................................................................................B-3 Glossary of Terms and Abbreviations Index
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Figures
Figure Number 1-1 2-1 3-1 5-1 5-2 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 8-1 8-2 8-3 A-1 B-1 B-2 B-3 Title Page Number
MC92602 Block Diagram ........................................................................................... 1-4 MC92602 Transmitter Block Diagram ....................................................................... 2-2 MC92602 Receiver Block Diagram............................................................................ 3-2 PLL Power Supply Filter Circuits............................................................................... 5-4 HSTL Class-I VREF Circuit ....................................................................................... 5-5 Instruction Register ..................................................................................................... 6-2 Device Identification Register..................................................................................... 6-3 Transmitter DDR Interface Timing Diagram .............................................................. 7-4 Receiver Interface DDR Timing Diagram .................................................................. 7-5 Reference Clock Timing Diagram .............................................................................. 7-6 Recovered Clock Timing Diagram.............................................................................. 7-7 Link Differential Output Timing Diagram .................................................................. 7-8 Link Differential Input Timing Diagram..................................................................... 7-8 JTAG I/O Timing Diagram.......................................................................................... 7-9 196 MAPBGA Nomenclature ..................................................................................... 8-2 196 MAPBGA Dimensions ........................................................................................ 8-3 196 MAPBGA Package .............................................................................................. 8-4 Motorola Part Number Key........................................................................................ A-1 Unencoded Transmission Character Bit Ordering ......................................................B-1 Encoded Transmission Character Bit Ordering ..........................................................B-2 Character Transmission...............................................................................................B-3
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Figures
ix
Figures
Figure Number Title Page Number
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MC92602 SERDES Reference Manual
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Tables
Table Number 1-1 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 3-7 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 B-1 B-2 Title Page Number
MC92602 SERDES Reference Manual Revision History .......................................... 1-5 MC92602 Transmitter Interface Signals ..................................................................... 2-3 Conversion of Transmitter Inputs to Internal Transmit Data (TBIE = low)................ 2-4 Conversion of Transmitter Inputs to Internal Transmit Data (TBIE = high) .............. 2-4 Transmitter Control States (TBIE=low)...................................................................... 2-5 Transceiver Disable - Channel Drop Sync Operation ................................................. 2-7 MC92602 Receiver Interface Signals ......................................................................... 3-3 Byte Synchronization Modes ...................................................................................... 3-6 Word Synchronization Settings................................................................................... 3-8 Byte Mode (TBIE = low) Receiver Outputs ............................................................. 3-10 10 Bit Mode (TBIE = high) Receiver Outputs.......................................................... 3-10 Receiver Interface Error Codes (Byte Interface, TBIE = low).................................. 3-11 Receiver Interface Error Codes (Ten-bit Interface, TBIE = high)............................. 3-11 Legal Reference Clock Frequency Ranges ................................................................. 5-1 Startup Sequence Step Duration ................................................................................. 5-2 Asynchronous Configuration and Control Signals...................................................... 5-3 TAP Interface Signals.................................................................................................. 6-1 Tap Controller Public Instructions .............................................................................. 6-2 Tap Controller Private Instruction Codes .................................................................... 6-2 Test Mode State Selection........................................................................................... 6-3 BIST Error Codes........................................................................................................ 6-4 Absolute Maximum Ratings ....................................................................................... 7-2 Recommended Operating Conditions ......................................................................... 7-2 DC Electrical Specifications ....................................................................................... 7-3 Transmitter DDR Timing Specification ...................................................................... 7-5 Receiver DDR Timing Specification........................................................................... 7-5 Reference Clock Specification .................................................................................... 7-6 Recovered Clock Specification ................................................................................... 7-7 Link Differential Output Specification........................................................................ 7-8 Link Differential Input Timing Specification.............................................................. 7-8 JTAG I/O Timing Specification................................................................................... 7-9 MC92602 Package Option Thermal Resistance Values .............................................. 8-5 196 Signal to Ball Mapping ........................................................................................ 8-5 Components of a Character Name ..............................................................................B-2 Valid Data Characters..................................................................................................B-4
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Tables
Table Number B-3 Title Page Number
Valid Special Characters .............................................................................................B-8
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About This Book
The primary objective of this reference manual is to describe the functionality of the MC92602 for software and hardware developers. Information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers' responsibility to be sure they are using the most recent version of the documentation.
Audience
It is assumed that the reader has the appropriate general knowledge regarding the design and layout requirements for high speed (Gbps) digital signaling and understanding of the basic principles of Ethernet and Fibre Channel communications protocols to use the information in this manual.
Organization
Following is a summary and a brief description of the major sections of this manual: * * * * * Chapter 1, "Introduction," gives an overview of the device features and shows a block diagram of the major functional blocks of the part. Chapter 2, "Transmitter," describes the MC92602 transmitter, its interfaces and operational options. Chapter 3, "Receiver," gives a description of the receiver. Chapter 4, "Rate Adaption of Packet Data Streams," describes how rate adaption is performed when receiving Ethernet packets. Chapter 5, "System Design Considerations," describes the system considerations for the MC92602, including clock configuration, device startup and initialization, and proper use of the configuration control signals. Chapter 6, "Test Features," covers the JTAG implementation and the system accessible test modes. Chapter 7, "Electrical Specifications and Characteristics," describes the DC and AC electrical characteristics.
* *
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About This Book
xiii
* * * *
Chapter 8, "Package Description," provides the package parameters and mechanical dimensions and signal pin to ball mapping tables for the MC92602 device. Appendix A, "Ordering Information," provides the Motorola part numbering nomenclature for the MC92602 transceiver. Appendix B, "8B/10B Coding Scheme," provides tables of the fibre channel-specific 8B/10B encoding and decoding is based on the ANSI FC-1 fibre channel standard. "Glossary of Terms and Abbreviations" contains an alphabetical list of terms, phrases, and abbreviations used in this book.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture and computer architecture in general: * The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, by International Business Machines, Inc. For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html. Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A. Patterson and John L. Hennessy
* *
Related Documentation
Motorola documentation is available from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: * Reference manuals--These books provide details about individual device implementations. The MC92602DVB Reduced Interface SERDES Design Verification Board Reference Manual (MC92602DVBRM/D) describes how to use the design verification board and should be read in conjunction with this manual, the MC92602 Quad 1.25 Gbaud Reduced Interface SERDES Reference Manual (MC92602RM/D). Addenda/errata to reference manuals--Because some devices have follow-on parts an addendum is provided that describes the additional features and functionality changes. These addenda are intended for use with the corresponding reference's manuals.
MC92602 SERDES Reference Manual MOTOROLA
*
xiv
*
* *
*
Hardware specifications--Hardware specifications provide specific data regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations. This manual contains all the hardware specifications for the MC92602. Application notes--These short documents address specific design issues useful to programmers and engineers working with Motorola processors. White Paper-These documents provide detail on a specific design platform and are useful to programmers and engineers working on a specific product. MC92610 3.125 Gbaud Reference Design Platform (BR1570/D) describes the technical design process used in developing a high-speed backplane reference design. Additional literature is published as new processors become available. For a current list of documentation, refer to http://www.motorola.com/semiconductors.
Conventions
This document uses the following notational conventions: Book titles in text are set in italics Internal signals are set in italics, for example, loop_back_data 0x 0b x x n Prefix to denote hexadecimal number Prefix to denote binary number In some contexts, such as signal encodings, an un-italicized x indicates a don't care. An italicized x indicates an alphanumeric variable. An italicized n indicates an numeric variable.
Signals
A bar over a signal name indicate that the signal is active low--for example, XMIT_A_IDLE and XMIT_B_IDLE. Active low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as XMIT_EQ_EN and DROP_SYNC are referred to as asserted when they are high and negated when they are low.
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About This Book
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MC92602 SERDES Reference Manual
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Chapter 1 Introduction
This reference manual explains the functionality of the MC92602 Quad 1.25 Gbaud Reduced Interface SERDES transceiver and enables its use by software and hardware developers. The audience for this publication, therefore, consists of hardware designers and application programmers who are building data path switches and high-speed backplane intercommunication applications. The remainder of this document will refer to the term reduced interface as DDR.
1.1
Overview
The MC92602 is a high-speed, full-duplex, serializer/deserializer (SERDES) data interface device that can be used to transmit data between chips across a board, through a backplane, or through cabling. The MC92602 has four transceivers that transmit and receive coded data at a rate of 1.0 gigabit per second (Gbps) through each 1.25 gigabaud link. The MC92602 is designed specifically for high-density board applications where reduction of interface signals is a primary concern. The MC92602 is built upon the proven transceiver technology in the Quad MC92600 device and is carefully designed for low power consumption. Its 0.25 CMOS implementation nominally consumes approximately 1.2 Watts with all links operating at full speed. Signal I/O count is reduced relative to the MC92600 device by operating the parallel interfaces at 125 MHz Double Data Rate (DDR) 4-bits wide per channel, per direction. HSTL class-I source terminated I/O is an accepted signalling method for 125 MHz DDR data for FR-4 board traces up to 8 inches. The MC92602 also includes the addition of transmit FIFOs and source-synchronous transmit clocks per channel to further simplify interfacing. This aggressive signaling scheme and packaging in a 196 pin fine pitch BGA offers excellent board density without making unreasonable signal integrity demands of the ASIC device to which it interfaces. An IEEE Std 802.3 - 2002 (R) compatibility mode has been included to enable non-intrusive operation with packet streams. And finally, IEEE Std 1149.1 TM JTAG boundary scan and built in PRBS generator/analyzers are provided for board test support.
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Chapter 1. Introduction
1-1
Features
1.2
*
Features
General Features -- Four full-duplex differential data links. -- Selectable speed range: 1.25 Gbaud or 0.625 Gbaud. -- Rate adaption compatibility with packet data streams -- Context sensitive rate adaption during receipt of idle and data code groups -- Supports Jumbo frame lengths of up to 16K BYTES -- Supports frame bursting -- Differential reference clock input with single-ended clock input option. -- Low power, approximately 1.2W under typical conditions, while operating all transceivers at full speed. -- Unused transceiver channels may be individually disabled. -- IEEE 1149.1 JTAG support and full-speed built in self test, (BIST), functions. -- Package: 196pin MAPBGA (15x15mm body size, 1.0 mm ball pitch). Data Interface Features -- Internal 8B10B encoder/decoder that may be bypassed in Ten-Bit Interface mode where external coding is used. -- Double Data Rate (DDR), source synchronous, 4-bit and 5-bit HSTL Class-I parallel interfaces. -- Transmit data clock is selectable between per-channel transmit clock or channel `A' transmit clock. -- Link-to-link synchronization supports aligned, multi-channel, word transfers. The synchronization mechanism tolerates up to 40 bit-times of link-to-link media skew. -- Selectable Idle character alignment mode enables aligned transfers with automatic realignment or unaligned data transfers (if in 10 bit mode). -- Received data may be clocked to the recovered clock or to the reference clock frequencies. -- Compatibility mode enables non-intrusive operation with packet data streams. Link Interface Features -- Drives 50 or 75 media (100 or 150 differential) for lengths of up to 1.5 meters board/backplane, or 10 meters of coax. -- Link inputs have on-chip receiver termination and are "hot swap" compatible. -- Tolerates a frequency offset between the transmitter and receiver in excess of +250ppm.
MC92602 SERDES Reference Manual MOTOROLA
The following are the features of the MC92602:
*
*
1-2
Block Diagram
1.3
Block Diagram
The MC92602 is a highly integrated device containing all of the logic needed to facilitate the application and test of a high-speed serial interface. No external components, other than the normal power supply decoupling network are required. A block diagram of the MC92602 device is shown in Figure 1-1.
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Chapter 1. Introduction
1-3
Block Diagram
XMIT FIFO XMIT_A_[3:0] XMIT_A_K XMIT_A_CLK BIST RECV_A_[3:0] RECV_A_K RECV_A_ERR RECV_A_CLK CLK GEN XMIT FIFO XMIT_B_[3:0] XMIT_B_K XMIT_B_CLK BIST RECV_B_[3:0] RECV_B_K RECV_B_ERR RECV_B_CLK RECV_REF_A, COMPAT,REPE,WSE. HSE, ADIE,TBIE,BSYNC LBE,LBOE,DROP_SYNC, TST_0,TST_1,STNDBY, RESET, XMIT_A_REF, MEDIA,RCCE TDI,TRST,TCK TDO XMIT_C_[3:0] XMIT_C_K XMIT_C_CLK RECV_C_[3:0] RECV_C_K RECV_C_ERR RECV_C_CLK BIST RECV FIFO 8B10B Decoder CLK GEN XMIT FIFO XMIT_D_[3:0] XMIT_D_K XLINK_D_N XLINK_D_P Transmitter 8B10B Encoder Receiver CLK GEN RECV FIFO 8B10B Decoder Receiver XLINK_B_N XLINK_B_P Transmitter 8B10B Encoder RECV FIFO 8B10B Decoder Receiver XLINK_A_N XLINK_A_P Transmitter 8B10B Encoder
XCVR_A_DISABLE
RLINK_A_P RLINK_A_N
XCVR_B_DISABLE
RLINK_B_P RLINK_B_N
LINK CONTROLLER
PLL
REF_CLK_P REF_CLK_N
JTAG CONTROLLER
XMIT FIFO XLINK_C_N Transmitter 8B10B Encoder
XLINK_C_P
XCVR_C_DISABLE
RLINK_C_P RLINK_C_N
XMIT_D_CLK BIST RECV_D_[3:0] RECV_D_K RECV_D_ERR RECV_D_CLK RECV FIFO 8B10B Decoder CLK GEN
XCVR_D_DISABLE Receiver
RLINK_D_P RLINK_D_N
Figure 1-1. MC92602 Block Diagram
1-4
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References
1.4
[1] [2] [3]
References
Fibre Channel, Gigabit Communications and I/O for Computer Networks, Brenner, 1996. Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code, U.S. Patent #4,486,739, Dec. 4, 1984. High Speed Transceiver Logic (HSTL), A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, EIA/JEDIC Standard EIA/JESD8-6, Aug. 1995. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-1990 (Includes IEEE Std. 1149.1a-1993), Oct. 1993. IEEE Standard Carrier Sense Multiple-Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Std. 802.3-2000.
This section contains the indexed references in the document.
[4] [5]
1.5
Revision History
Table 1-1. MC92602 SERDES Reference Manual Revision History
Table 1-1 contains a brief description of the technical updates made to this document.
Revision Level 0
Change First release of the MC92602 SERDES reference manual.
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Chapter 1. Introduction
1-5
Revision History
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Chapter 2 Transmitter
This chapter describes the MC92602 transmitter, its interfaces and operation. The chapter consists of the following sections: * * * Section 2.1, "Transmitter Block Diagram" Section 2.2, "Transmitter Interface Signals" Section 2.3, "Functional Description."
The transmitter takes data presented at its source synchronous parallel data input port, creates an encoded transmission character (if not pre-encoded), and serially transmits the character out of the differential link output pads. A detailed explanation of the 8B/10B coding scheme is offered in Appendix B, "8B/10B Coding Scheme."
2.1
.
Transmitter Block Diagram
Figure 2-1 shows a block diagram of the MC92602 transmitter.
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Chapter 2. Transmitter
2-1
Transmitter Interface Signals
MEDIA
Serialization Register (loop_back) (xmit_en) XMIT Controller (8b/10b)
XLINK_x_P XMIT Driver XLINK_x_N
XCVR_x_DISABLE
8B/10B Encoder loop_back_data rx_clock XMIT FIFO
LBE, LBOE
TBIE, REPE
BIST repeat_data XMIT_REF_A XMIT_A_CLK XMIT_x_CLK Sequence Generator
Input Reg.
Input Reg.
XMIT_x_[3:0] XMIT_x_K
Figure 2-1. MC92602 Transmitter Block Diagram
2.2
Transmitter Interface Signals
This section describes the interface signals of the MC92602 transmitters. Each signal is described, including its name, function, direction, and active state in Table 2-1. The table's signal names use the letter "x" as a place holder for the Link identifier letter "A" through "D". Internal signals are not available at the I/O of the device, but are presented to illustrate device operation.
2-2
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Transmitter Interface Signals
Table 2-1. MC92602 Transmitter Interface Signals
Signal Name XMIT_x_3 through XMIT_x_0 Description Transmit Nibble Function If TBIE is low these are 4 bits of uncoded data to transmit. Bits 3 through 0 on rising edge of clock. Bits 7 through 4 on falling edge of clock. If TBIE is high these 4 bits are coded data to transmit. Bits 3 through 0 on rising edge of clock. Bits 8 through 5 on falling edge of clock. If TBIE is low this is the "K" (special char) input on the rising edge of clock and the IDLE (Idle indicator) on the falling edge of clock. If TBIE is high this is data bit 4 on the rising edge of clock and data bit 9 on the falling edge of clock Clock to which transmit interface signals are timed. Direction Input Active State -
XMIT_x_K
Transmit Control Bit
Input
-
XMIT_x_CLK XMIT_REF_A
Channel Transmit Clock
Input Input
High
Transmit Interface Clock Indicates that the transmit interface Select signals are timed to XMIT_A_CLK instead of their own transmit clock. Transceiver Disable Indicates that the transmitter and receiver for this transceiver are disabled. The link outputs are not driven. (see Section 2.3.4 for details).
XCVR_x_DISABLE
Input
High
TBIE
Ten-Bit Interface Enable Indicates that pre-coded 10-bit data is at inputs and to bypass internal 8B/10B coding. Repeater Mode Enable Half Speed Enable Test feature only. Must be disabled (low) during normal operation. When enabled, link is operated at half-speed. Both data and link interfaces run at half speed. Activate digital loopback path, such that data transmitted is looped back to its receiver. Indicates that link outputs remain active when LBE is asserted. When LBOE is low, link outputs are disabled when LBE is asserted. Decoded to define various test modes (see Chapter 6 for details).
Input
High
REPE HSE
Input Input
High High
LBE
Loop Back Enable
Input
High
LBOE
Loop Back Output Enable
Input
High
TST_1, TST_0 MEDIA
Test mode config inputs
Input Input
-
Media Impedance Select Indicates the impedance of the transmission media. Low indicates 50 and high indicates 75.
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Chapter 2. Transmitter
2-3
Functional Description
Table 2-1. MC92602 Transmitter Interface Signals (continued)
Signal Name XLINK_x_N/ XLINK_x_P Internal Signals rx_clock repeat_data loop_back_data High Speed Transceiver Clock Repeater Data Loop Back Data Internal, differential high speed clock used to transmit and receive link data. Internal data from the receiver to be used when REPE is active. Differential loop back transmit data. Input Input Output Description Function Direction Output Active State -
Link Serial Transmit Data Differential serial transmit data output pads.
2.3
Functional Description
The transmitter takes the data byte presented at its data input, creates a transmission character using its 8B/10B encoder (if not in Ten-Bit Interface mode), and serially transmits the character out of the differential link output pads. The following sections provide a detailed description of the transmitter and its various modes of operation.
2.3.1
Transmit Data Input Register Operation
Transmit data is sampled and stored in the input register on the rising and falling edge of the appropriate transmit clock. This results in the accumulation of 10 transmit bits per complete clock cycle. The transmit data input register accepts data to be transmitted and synchronizes it to the internal clock domain. Transmit data may be uncoded 8-bit data or coded 10-bit data, depending upon the state of the control input, TBIE. The Ten-Bit Interface mode, TBI, is enabled by asserting Ten-Bit Interface Enable, TBIE, high. Table 2-2 and Table 2-3 describe the meaning of each transmit data bit depending upon the state of TBIE.
Table 2-2. Conversion of Transmitter Inputs to Internal Transmit Data (TBIE = low)
Clock Edge Rising Falling XMIT_x_K K Idle XMIT_x_3 Data Bit 3 Data Bit 7 (MSB) XMIT_x_2 Data Bit 2 Data Bit 6 XMIT_x_1 Data Bit 1 Data Bit 5 XMIT_x_0 Data Bit 0 (LSB) Data Bit 4
Table 2-3. Conversion of Transmitter Inputs to Internal Transmit Data (TBIE = high)
Clock Edge Rising Falling XMIT_x_K Data Bit 4 Data Bit 9 (MSB) XMIT_x_3 Data Bit 3 Data Bit 8 XMIT_x_2 Data Bit 2 Data Bit 7 XMIT_x_1 Data Bit 1 Data Bit 6 XMIT_x_0 Data Bit 0 (LSB) Data Bit 5
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2.3.1.1
Transmitting Uncoded Data
If TBIE is low the transmit data is to be treated as uncoded 8 bit data, that must be encoded by the on-chip 8B/10B encoder. 8B/10B coding ensures DC balance across the link and sufficient transition density to facilitate reliable data recovery. The state of XMIT_x_K on the rising edge of the transmit clock will be referred to as the "K" bit. The state of XMIT_x_K on the falling edge of the transmit clock will be referred to as the "Idle" bit. Data transmitted as a function of these two bits are as indicated in Table 2-4. If K is low this 8 bit data is then coded into a 10-bit data character. If K is high and Idle is low, then the remaining data bits are ignored and the on-chip 8B/10B encoder creates an IDLE character (K28.5) with the appropriate disparity. Special control codes may be transmitted by asserting K high, and Idle high The transmit byte is assumed to be a control code in this state.
Table 2-4. Transmitter Control States (TBIE=low)
IDLE Don't care Low High K Low High High Description Transmit data present on internal Data Bits 7 through 0. Transmit Idle (K28.5), ignore internal Data Bits 7 through 0. Transmit control present on internal Data Bits 7 through 0.
2.3.1.2
Transmitting Coded Data
Ten-bit coded data may be transmitted, bypassing the internal 8B/10B encoder. The Ten-Bit Interface, TBI, mode is enabled by asserting TBIE high. In this mode, the ten bits of data to transmit are presented on the internal Data Bits 9 through 0 as previously shown in Table 2-3. Special care must be taken when using TBI mode. The 10-bit pre-coded data must exhibit the same properties as 8B/10B coded data. DC balance must be maintained and there must be sufficient transition density to ensure reliable data recovery at the receiver. The receiver requires that the K28.5 Idle character be periodically transmitted to enable byte and word synchronization. This 10-bit pattern, `0011111010' or `1100000101' (ordered from least significant bit, bit-0, through most significant bit, bit-9) is used for alignment and channel synchronization when operating in any of the byte or word synchronization modes. The pattern of Idles and data required to achieve byte or word synchronization depends on the configuration of the receiver. The appropriate sequence must be applied through the Ten-Bit Interface.
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Functional Description
2.3.1.3
Transmit Interface Clock Configuration
The transmitter data interface operates at high frequency (up to 125MHz double data rate). Data is clocked into the transmitter on both the rising and falling edges of the transmit clock. In order to ease development of devices that interact with the MC92602, all of its data interfaces are source-synchronous. The data for each transmitter has its own dedicated clock input. This allows the clock at the source of the data to be routed with the data ensuring matched delay and timing. However, if per-transmitter clock sources are not available or deemed unnecessary, all transmitters may be clocked by a common clock source. This is enabled by asserting XMIT_REF_A high. When XMIT_REF_A is high, the XMIT_A_CLK becomes the interface clock for all active channels. The configuration settings of the MC92602 affect the legal range of clock frequencies at which it may be operated. Table 5-1 shows legal transmit interface clock frequencies for all modes of operation. All transmit interface clock inputs, XMIT_x_CLK, and the PLL reference clock, REF_CLK, inputs must have identical frequencies. The transmit data interface tolerates +180o of transmit interface clock phase drift relative to the PLL reference clock.
2.3.2
8B/10B Encoder Operation
The 8B/10B Encoder encodes 8-bit data/control from the input register into 10-bit transmission characters. The Fibre Channel 8B/10B coding standard is followed [1,2]. Running disparity is maintained and the appropriate transmission characters are produced, maintaining DC balance and sufficient transition density to allow reliable data recovery at the receiver. The inputs to the 8B/10B Encoder are the data byte (internal Data Bits 7 through 0), special code signal (K) and transmit idle signal (IDLE). Data and legal control bytes are coded according to the 8B/10B method. Illegal control bytes produce unpredictable transmission characters, which may lead to disparity and coding errors, thereby reducing link reliability. The 8B/10B encoder produces an Idle character (K28.5) of proper running disparity when K is high and IDLE is low, as indicated in Table 2-4. The 8B/10B Encoder is bypassed if TBIE is asserted high.
2.3.3
Transmit Driver Operation
The Transmit Driver drives transmission characters serially across the link. Two bits per transceiver clock, one each on the rising and falling transceiver clock (rx_clock) edges, are transmitted differentially from the XLINK_x_P/XLINK_x_N outputs. The internal rx_clock runs at 625 MHz for 1 Gbps (1.25 Gbaud) operation and 312.5 MHz for 500 Mbps (625 Mbaud) operation.
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Functional Description
The Transmit Driver is a controlled impedance driver. The impedance of the driver is programmable to 50 or 75 through the MEDIA signal. Drive impedance is 50 when the control signal, MEDIA, is low and 75 when MEDIA is high.
2.3.4
Transceiver Disable
Each individual transceiver may be disabled with the appropriate XCVR_x_DISABLE signal. The XCVR_x_DISABLE control signal also has a secondary function when used in association with the receiver control signal DROP_SYNC that allows external forcing of loss of byte synchronization on an individual channel basis. The relationship of these two control signals is shown in Table 2-5.
Table 2-5. Transceiver Disable - Channel Drop Sync Operation
XCVR_x_DISABLE low high low high DROP_SYNC low low high high ACTION Transceiver Channel Active - normal operation Transceiver channel "x" disabled Transceiver channel active - normal operation Transmitter "x" active; Receiver "x" is forced to "Drop Sync"
When Drop_Sync is high, XCVR_x_DISABLE has no effect on the function of the transmitter. Rather when asserted high it is used to perform the loss of synchronization on the selected channel NOTE Since DROP_SYNC and XCVR_x_DISABLE are asynchronous signals (relative to the internal clocks) they must be asserted for two or more cocks. DROP_SYNC should be raised prior to XCVR_x_DISABLE and lowered after XCVR_x_DISABLE. To assure proper action raise DROP_SYNC on clock #1, raise XCVR_x_DISABLE on clock #2, lower XCVR_x_DISABLE on Clock #n (n must be 4 or greater), then lower DROP_SYNC on Clock #n+1.
2.3.5
Loop-Back Test Mode
A special loop-back mode is supported for test. Asserting LBE high, enables loop-back mode causing the data being driven on the link outputs to be looped back, internally, to the input amplifier of the link's receiver. Loop-back data is processed the same as normally received data. Loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. The loop-back signals are electrically isolated from the link output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally.
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Functional Description
When in loop-back mode, the loop-back output Enable signal, LBOE, controls the action of the link output signals. When LBOE is low, the link outputs are undriven and are high-impedance. When LBOE is high, the link output signals operate normally. LBOE has no affect on the operation of the device when LBE is low. See Section 6.2 for more information on system accessible test modes.
2.3.6
Repeater Mode
Repeater mode is not recommended for application use. It is used for factory engineering and manufacturing test purposes only. The repeater enable signal, REPE, should be configured low during normal operation.
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Chapter 3 Receiver
This chapter describes the MC92602 receiver, its interfaces, and operation. This chapter has the following sections: * * * Section 3.1, "Receiver Block Diagram" Section 3.2, "Receiver Interface Signals" Section 3.3, "Functional Description"
The receiver is a dual data rate receiver, operating at 1Gbps or 500Mbps rates (1.25 or 0.625 Gbaud) and is based upon an oversampled transition tracking loop data recovery method. The receiver takes a high speed differential serial data stream input, over samples it and recovers the data and clock, decodes it and presents it on a source synchronous, double data rate, reduced interface (5-bit) output data port.
3.1
Receiver Block Diagram
Figure 3-1 shows a block diagram of the MC92602 receiver.
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Receiver Interface Signals
MEDIA loop_back_data
RLINK_x_P RLINK_x_N LBE HSE BSYNC DROP_SYNC
RECV Amp
Delay Line
rx_clock
Idle Detection and Byte Alignment
Transition Tracking Loop and Data Recovery
recv_byte_clock idle_detect
8B10B Decoder
TBIE
TST_0 Word Alignment WSE Alignment FIFO TST_1
drop/add REF_CLK Timing Alignment RCCE, REPE RECV_REF_A ADIE COMPAT BIST/BERT Analyzer repeat_data RECV_x_[3:0] Receiver Interface RECV_x_K RECV_x_ERR
RECV_x_CLK
Figure 3-1. MC92602 Receiver Block Diagram
3.2
Receiver Interface Signals
This sections describes the interface signals of the MC92602 receiver. Each signal is described, including its name, function, direction and active state in Table 3-1. The table's signal names use the letter "x" as a place holder for the link identifier letter "A" through
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Receiver Interface Signals
"D". Internal signals are not available at the I/O of the device, but are presented to illustrate device operation.
Table 3-1. MC92602 Receiver Interface Signals
Signal Name Description Function If TBIE is low these are 4 bits of uncoded data received. Bits 3 through 0 on rising edge of clock. Bits 7 through 4 on falling edge of clock. If TBIE is high these 4 bits are coded data received. Bits 3 through 0 on rising edge of clock. Bits 8 through 5 on falling edge of clock. If TBIE is low, both rising edge and falling edge states are used to encode status out. See Table 3-4. If TBIE is high this is data bit 4 on rising edge and data bit 9 on falling edge. Receiver status out. If TBIE is low it is used in conjunction with RECV_x_K. If TBIE is high then it is the only status bit. See Table 3-6 and Table 3-7. Internally generated clock used for reading receiver outputs. This signal may be derived from the REF_CLK, receiver A's recovered clock, or this receiver's recovered clock. Direction Output Active State -
RECV_x_3 through Received Nibble RECV_x_0
RECV_x_K
Special Data Indicator
Output
-
RECV_x_ERR
Receiver Error
Output
-
RECV_x_CLK
Receiver Clock
Output
-
TBIE
Ten-Bit Interface Enable Indicates that the Receiver Interface is in ten-bit mode and that the 8B/10B decoder is bypassed. Half Speed Enable Indicates to operate link at half-speed. Both data and link interfaces run at half speed. Indicates that all enabled receivers are being used in unison to receive synchronized data. Indicates that byte alignment is required, if low no byte alignment is done.
Input
High
HSE
Input
High
WSE
Word Synchronization Enable Byte Alignment Mode
Input
High
BSYNC RCCE REPE RECV_REF_A
Input Input Input Input
High High High
Recovered Clock Enable Indicates that the output data is synchronized to a recovered byte clock. Repeater Mode Enable Test feature only. Must be disabled (low) during normal operation.
Receiver A Clock Enable Indicates that if RCCE is also high that the data will be synchronized to Channel A's recovered clock.
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Functional Description
Table 3-1. MC92602 Receiver Interface Signals (continued)
Signal Name ADIE Description Add/Delete Idle Enable Function Indicates that the receiver is free to add/delete Idle characters to/from the output data stream to maintain alignment. Special character addition and deletion rules are followed in compatibility mode. See section 3.3.7.2 for more information. Indicates that the receiver follows special character addition and deletion rules to maintain alignment that are non-intrusive to packet data streams. SeeChapter 4, "Rate Adaption of Packet Data Streams," for more information. Indicates that data into the receiver is to be taken from the local transmitter instead of the RLINK_n_P/N inputs. Enables control such that current byte and word alignment be invalidated and new alignment acquired. DROP_SYNC enables XCVR_x_DISABLE to force loss of alignment. Direction Input Active State High
COMPAT
Compatibility Mode Enable
Input
High
LBE
Enable Loopback
Input
High
DROP_SYNC
Drop Synchronization Enable
Input
High
XCVR_x_DIASABLE XCRV Disable or channel Asserted when DROP_SYNC is high will drop sync. invalidate current byte and word alignment. (see Section 2.3.4) TST_0/ TST_1 REF_CLK_P/N Test Mode PLL Reference Clock Indicates operating/test mode of the chip. See Chapter 6. PLL input reference clock. Provides reference frequency for the receiver interface when Recovered Clock mode is disabled (RCCE is low).
Input
High
Input Input
-
RLINK_x_N/ RLINK_x_P
Link Serial Receive Data Differential serial receive data input pads. Internal Signals
Input
-
rx_clock loop_back_data repeat_data
High Speed Clock Loop Back Data Repeater Data
Internal, differential high speed clock used to transmit and receive link data. Differential loop back receive data. Data received that is available to the transmitter if in repeater mode (REPE is high)
Input Input Output
-
3.3
Functional Description
The MC92602 receiver receives differential data in one of two operating ranges. It may be operated in full rate range with a maximum data rate of 1.0 Gbps (1.25 gigabaud) or at
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Functional Description
half-rate at 500 Mbps (0.625 gigabaud). The operating range is determined by the state of the HSE input and the frequency of the reference clock, see Table 5-1. Transmitted data is recovered using an oversampled transition tracking method. The received serial data is accumulated into ten-bit characters. The ten-bit characters are forwarded to the 8B/10B decoder where the original data is obtained. Alternately, the decoder can be bypassed and the ten-bit character is forwarded to the Receiver Interface in the ten-bit interface (TBI) mode. The receiver provides for byte (character) alignment. Alignment assures that the byte as presented at the input of the transmitter is preserved when the byte is presented by the receiver. Optionally, alignment may be disabled. The receiver also provides for word synchronization. In this mode, all of the receivers are being used cooperatively to receive 32-bit (40 bit in TBI mode) words. Word synchronization assures that the receivers present the four bytes of a word simultaneously. The Receiver Interface, where the received bytes and status codes are obtained, has several modes of operation and timing to allow it to be used in a variety of applications. The following sections provide a detailed description of the receiver and its modes of operation.
3.3.1
Input Amplifier
The input amplifiers connect directly to the link input pads RLINK_x_P and RLINK_x_N. It is a differential amplifier with integrated analog multiplexer for loop-back testing. Link termination resistors are integrated with the amplifier. The termination resistance is either 100 or 150 differential depending upon the state of the MEDIA input. The input amplifier facilitates a loop-back path for production and in-system testing. When the MC92602 is in loop-back mode (Loop Back Enable, LBE, is high), the input amplifier selects the loop-back differential input signals and ignores the state on the RLINK_x_P and RLINK_x_N signals. This allows in-system loop-back BIST independent of the current input state. See Chapter 6 for more information on test modes.
3.3.2
Transition Tracking Loop and Data Recovery
The received differential data from the input amplifier is sent to the transition tracking loop for data recovery. The MC92602 uses an oversampled transition tracking loop method for data recovery. The differentially received data is sampled and processed digitally providing for low bit error rate (better than 10 -12) data recovery of a distorted bit stream. The transition tracking loop is tolerant of frequency offset between the transmitter and receiver. The MC92602 reliably operates with +250 ppm of frequency offset. The transition tracking loop method is different than the typical PLL clock recovery method. Its receiver compensates for overrun and underrun due to frequency offset by modulating the
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Functional Description
duty-cycle and period of the received byte clock such that it matches the frequency of the received data (see Section 3.3.7.1 for more information). Recovered data is accumulated into 10-bit characters. The characters are aligned to their original 10-bit boundaries if a Byte Alignment mode is enabled.
3.3.3
Byte Alignment
The receiver supports two modes of Byte Alignment as defined by the BSYNC signal. Table 3-2 shows the settings to activate each mode.
Table 3-2. Byte Synchronization Modes
Byte Alignment Mode Byte Aligned Non-Aligned BSYNC High Low
3.3.3.1
Byte-Aligned
At power-up, the receiver starts an alignment procedure, searching for the 10-bit pattern defined by the 8B/10B Idle code. Synchronization logic checks for the distinct Idle sequence, `0011111010' and `1100000101' (ordered bit 0 to bit 9), characteristic of the K28.5 Idle pattern. The search is done on the 10-bit data in the receiver, and is therefore independent of the TBIE input. Alignment requires a minimum of four, error-free, received Idle characters to ensure proper alignment and lock. Non-Idle characters may be interspersed with the Idle characters. The disparity of the Idle characters is not important to alignment and can be positive, negative or any combination. The receiver begins to forward received characters once locked on an alignment. However, if Word Synchronization Enable is asserted, WSE=high, received characters are not forwarded to the Receiver Interface until the first, valid, non-idle character is received. Alignment remains locked until any one of three events occur that indicate loss of alignment: * Alignment is lost when a misaligned Idle sequence is detected. A misaligned Idle sequence is defined as four Idle characters with an alignment different than the current alignment. Non-Idle characters may be dispersed between the four misaligned Idles, however, a properly aligned Idle character breaks the sequence. Although alignment is lost by this condition, the receiver automatically changes alignment to the newly detected alignment. However, status out will be reported as "Not Byte Sync" as described in Section 3.2.6.6 for a few recovered clocks to allow the receiver FIFO to re-align. Data will be lost while "Not Byte Sync" status is being reported. The actual number of clocks that "Not Byte Sync" will be reported will vary depending upon the number of bytes in the FIFO when realignment occurs.
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*
*
Alignment is also lost when the number of received characters with 8B/10B coding errors outnumbers the non-errored characters by four. Credit for non-errored characters in excess of errored characters is limited to four, such that alignment is lost after four consecutive errored characters. Misalignment detection of this type is not available in TBI mode. The receiver restarts its alignment procedure and halts data flow until a new alignment is established. Alignment is lost when DROP_SYNC followed by XCVR_x_DISABLE are both asserted high for at least two clocks (see Section 2.3.4 for details on performing drop sync). Current alignment is invalidated, the receiver restarts its alignment procedure and halts data flow until a new alignment is achieved.
When establishing byte alignment, or when data flow is halted due to misalignment, the "Not Byte Sync" error is reported as described in Section 3.3.6.3.
3.3.3.2
Non-Aligned
In this mode no attempt is made to align the incoming data stream. The bits are simply accumulated into 10-bit characters and forwarded. This mode should be used only with Ten-Bit Interface mode, TBIE set high, and with Word Synchronization disabled, WSE set low.
3.3.4
Word Synchronization
The four receivers in the MC92602 can be used cooperatively to receive aligned multi-channel word transfers. Word alignment is enabled by asserting Word Synchronization Enable input, WSE, high. Word synchronization is possible in Byte Interface mode or in TBI mode. However, word synchronization is dependent on the detection of simultaneously transmitted word synchronization events that contain Idle characters. Therefore, if operating in TBI mode, the Idle character must be a supported member of the code set. If WSE is high, then all enabled receivers (those that have XCVR_x_DISABLE set low) will be aligned into a 16, 24, or 32 bit word (depending upon the states of the various XCVR_x_DISABLE signals). If the receiver on Channel A is disabled, then do not select the clock from Channel A as the recovered clock for all the channels. The word synchronization event is four (or more) consecutive (K28.5) Idles followed by a non-Idle. Word synchronization events must be generated at all concerned transmitters simultaneously in order for synchronization to be achieved. Word synchronization events must be received at all concerned receivers within 40 bit-times of each other. Word synchronization events are used to establish a relationship between the received bytes in each of the receivers. The bytes of a word are matched and presented simultaneously at the Receiver Interface. Once synchronization is achieved the receiver tolerates +6 bit-times
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Functional Description
of drift between receivers. If drift exceeds +6 bit-times the receiver will continue to operate. However, the received bytes will no longer be synchronized properly because the receiver remains locked on the initially established synchronization. Word synchronization remains locked until an event occurs that indicates loss of synchronization. Word synchronization lock is lost when one or more of the receivers change or lose byte alignment (byte alignment loss is described in Section 3.3.3.1). Lock is also lost when overrun/underrun is detected on one or more of the receivers, see Section 3.3.7.1 for more about overrun/underrun. Word synchronization lock is lost when explicitly invalidated by asserting DROP_SYNC and XCVR_x_DISABLE high for at least two clocks (see Section 2.3.4 for details on performing drop sync). When lock is lost, word synchronization must be re-established before data flow through the receiver resumes. The Receiver Interface is disabled during initial word synchronization. No data is produced at its outputs until word synchronization is achieved and the first non-idle character is received. When establishing word synchronization, or when word synchronization is lost, "Not Word Sync" error is reported as described in Section 3.3.6.3.
3.3.4.1
Recommended Settings for Word Synchronization
Word synchronization can only be used with certain operating modes and has limited application in others. Table 3-3 describes the relationship between modes and word synchronization.
Table 3-3. Word Synchronization Settings
Mode Word Synchronization Byte Synchronization BSYNC Add/Delete Idle High Signals WSE Recommended State High High Description Enables word synchronization. Word synchronization depends upon Idle character detection. Byte alignment is required for Idle detection. When enabled, allows the receiver to add/delete Idle patterns in order to maintain word synchronization. This is the recommended operating mode when the Reference Clock is used to time the receiver interface (RCCE set low) and there is a frequency offset between the transmitter and receiver. Idles are added or dropped to maintain word alignment. Word synchronization is not supported in compatibility mode. When enabled, the Idle character must be part of the TBI code set. When disabled, the Idle is naturally supported by the 8B/10B codes.
ADIE
ICompatibility Mode Ten-Bit Interface
COMPAT
Low n/a
TBIE
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Table 3-3. Word Synchronization Settings (continued)
Mode Recovered Clock Receiver A recovered Clock select Signals RCCE RECV_REF_A Recommended State n/a High (if RCCE is high) Description Does not affect word synchronization. RECV_REF_A must be high if RCCE is enabled. The receiver A's recovered clock must be used for all receivers. The data at the receiver interfaces will be skewed if the individual receiver recovered clocks are used to time the receiver interfaces. Does not affect word synchronization.
Half-Speed Enable
HSE
n/a
3.3.5
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the Transition Tracking Loop and decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of error checking. First it checks that all characters are a legal member of the 8B/10B coding space. The decoder also checks for running disparity errors. If the running disparity exceeds the limits set in the 8B/10B coding standard then a disparity error is generated. An illegal character or disparity error results in a "Code Error" or "Disparity Error" being reported as described in Section 3.3.6.3. It is difficult to determine the exact byte that causes a disparity error, so the error should not be associated with a particular received byte. It is rather a general indicator of the improper operation of the link. Its intended use is for the system to monitor link reliability. The 8B/10B decoder is bypassed when operating in Ten-Bit Interface mode (TBIE set high.) NOTE 8B/10B coding is meant only to improve data transmission characteristics and is not a good error detection code. Many 8B/10B characters alias to other valid 8B/10B characters in the presence of bit errors. Error detection and correction techniques must be applied outside of the MC92602 if better than 10-12 bit error rate is required.
3.3.6
Receiver Interface
Data in the alignment FIFO is presented at the Receiver Interface as double data rate, DDR, on the rising and falling edge of the appropriate receiver clock, RECV_x_CLK. Along with the data, information is also provided on the status of the link. Table 3-1 describes each of the signals involved in receiver operation.
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Functional Description
The Receiver Interface, through which received data is obtained, may be operated in Byte mode or in Ten-Bit Interface mode. There are several timing mode options for the receiver interface. Each of the operating modes are described below.
3.3.6.1
Byte Interface
The Receiver Interface may be operated in Byte mode or in Ten-Bit Interface, TBI, mode. Received data is a byte (8 bits) of uncoded data when in Byte mode. The internal 8B/10B decoder is used to decode data from the 10-bit character received. Byte interface mode is enabled by setting TBIE low. Table 3-4, shows how data and status will appear on the receiver interface when in Byte Mode.
Table 3-4. Byte Mode (TBIE = low) Receiver Outputs
Clock Edge RECV_x_ERR RECV_x_K Rising Falling E0 E1 K0 K1 RECV_x_3 Data Bit 3 Data Bit 7 (MSB) RECV_x_2 Data Bit 2 Data Bit 6 RECV_x_1 Data Bit 1 Data Bit 5 RECV_x_0 Data Bit 0 (LSB) Data Bit 4
NOTE Do not use Non-Aligned mode in Byte mode. Non-aligned mode is only valid if TBIE is high.
3.3.6.2
Ten-Bit Interface
Received data is ten-bits of pre-coded data when in the Ten-Bit Interface, TBI, mode. The internal 8B/10B decoder is not used and it is assumed that decoding is done externally. Ten-Bit Interface mode is enabled by setting TBIE high. Table 3-5, shows how data and status will appear on the receiver interface when in 10-bit mode.
Table 3-5. 10 Bit Mode (TBIE = high) Receiver Outputs
Clock Edge RECV_x_ERR Rising Falling E0 E1 RECV_x_K Data Bit 4 Data Bit 9 (MSB) RECV_x_3 Data Bit 3 Data Bit 8 RECV_x_2 Data Bit 2 Data Bit 7 RECV_x_1 Data Bit 1 Data Bit 6 RECV_x_0 Data Bit 0 (LSB) Data Bit 5
3.3.6.3
Receiver Interface Error Codes
The receiver's status and data error conditions are coded on the RECV_x_ERR and RECV_x_K signals (see Table 3-4 and Table 3-5).
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Functional Description
When in Byte mode (TBIE is low) E0, E1, K0, and K1 indicate the receiver operating status. Table 3-6 describes the encoding and meaning of the status and error conditions for Byte mode.
Table 3-6. Receiver Interface Error Codes (Byte Interface, TBIE = low)
E0 Low Low Low Low Low Low Low High High E1 Low Low Low High High High High Low High K0 Low High High Low Low High High Don't care Don't care K1 Don't care Low High Low High Low High Don't care Don't care Priority 8 7 6 4 5 3 3 1 2 Description Normal operation, valid data character received. Normal operation, valid control character received. Normal operation, valid Idle (K28.5) character received. Code Error: The 8B/10B decoder detected an illegal character. Disparity Error: The 8B/10B decoder detected a disparity error. Underrun: The receiver interface synchronization logic detected an underrun condition. Data has been repeated. Overrun: The receiver interface synchronization logic detected an overrun condition. Data has been dropped. Not Byte Sync: The receiver is in start-up or has lost byte alignment and is searching for alignment. Not Word Sync: The receiver is byte synchronized but has not achieved or has lost word synchronization and is searching for synchronization.
When in 10-bit mode (TBIE is high) E0, and E1 indicate the receiver operating status. Table 3-7describes the encoding and meaning of the status and error conditions for TBI mode.
Table 3-7. Receiver Interface Error Codes (Ten-bit Interface, TBIE = high)
E0 Low Low High High E1 Low High Low High Priority 4 3 1 2 Description Normal operation, non-Idle character received. Normal operation, Idle (K28.5) character received. Overrun/Underrun: The receiver interface synchronization logic detected and overrun/underrun condition. Data may be dropped or repeated. Not Byte/Word Sync: The receiver is in start-up or has lost byte or word alignment and is searching for alignment.
The Priority column in the tables show the error that is reported if multiple errors occur at the same time. The lower the Priority numbered errors are reported first.
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Functional Description
3.3.7
Receiver Interface Clock Timing Modes
The receiver interface is double data rate, source synchronous. Each of the receiver's six output signals are timed relative to the rising and falling edges of the receiver interface clock output, RECV_x_CLK. The receiver interface clock frequency may be selected between its own recovered clock frequency, receiver A's recovered clock frequency, or the frequency of the reference clock input REF_CLK. The recovered clock enable signal, RCCE, determines if the receiver interface is timed to the recovered clock or to the local reference clock. Asserting RCCE enables timing relative to the recovered clock, and set low enables timing relative to the reference clock. When RCCE is asserted high, then the signal RECV_REF_A is used to select the recovered clock to be used. If RECV_REF_A is asserted then Channel A's recovered clock is used for all four channels. If it is low then each channel uses its own recovered clock. The receiver interface clock signals, RECV_x_CLK, will always be present when the PLL is in lock. This is true even if there is no signal present on the serial inputs or if the receiver has not achieved alignment or byte sync. The frequency of the receiver clock will be the local reference clock. The clock signals however, are not present during power up or when the MC92602 is in reset mode and the PLL is not locked.
3.3.7.1
Recovered Clock Timing Mode
With RCCE asserted, the recovered clock signal, RECV_x_CLK, is generated by the receiver and, on average, runs at the reference clock frequency of the transmitter at the other end of the link. The recovered clock is not generated by a clock recovery PLL, but is generated by the receiver bit-accumulation and byte-alignment logic. In order to track a transmitter frequency that is offset from the receiver's reference clock frequency, the duty cycle and period of the recovered clock is modulated. The MC92602 is designed to tolerate up to a 250 ppm of frequency offset between transmitter and receiver. For example: If the transmitter is sending data at a rate faster than the receiver, then a shortened cycle is generated as needed to track the incoming data rate. Alternately, if the transmitter is running slower than the receiver, then a long cycle is generated. The recovered clock duty cycle may be reduced or increased by 2.5% in order to match the transmitter frequency. For example, if the reference clock frequency is 125MHz, this means that the minimum recovered clock cycle time is 7.8ns and the maximum recovered clock cycle is 8.2ns. NOTE Devices that interface to a MC92602 that is run in recovered clock mode must be able to tolerate this modulated clock.
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Functional Description
All receiver channel outputs are source synchronous with their respective RECV_x_CLK outputs. If the receivers are being operated in word synchronization mode (WSE = high), the data for all four receivers are timed relative to link A's recovered clock RECV_A_CLK. In word synchronization all four clocks are derived from channel A and may be used if necessary. When operating in the recovered clock timing mode, the addition or deletion of Idles is inappropriate. NOTE If RCCE is asserted (recovered clock timing mode), the add/delete idle enable (ADIE) signal must be low.
3.3.7.2
Reference Clock Timing Mode
Data is timed relative to the local reference clock frequency when RCCE is low. Synchronization between the recovered clock and the reference clock is handled by the receiver interface. Frequency offset between the transmitter's reference clock and the receiver's reference clock causes overrun/underrun situations. Overrun occurs when the transmitter is running faster than the receiver. Underrun occurs when the transmitter is running slower than the receiver. In an overrun situation, data must be dropped in order to maintain synchronization between the clock domains. If the control signal, add drop idle enable, ADIE, is asserted high, the receiver interface searches for a pair of idle bytes to drop when overrun is imminent. Two idle bytes are dropped to assure that running disparity is not affected. If sufficient idle patterns are not available to drop, receiver overrun may occur. When overrun occurs, the "Overrun" error is reported as described in Section 3.3.6.3, for one byte clock period and one character of data is dropped. An overrun error is also reported if ADI mode is disabled and overrun occurs, even if Idles are available to drop. NOTE The compatibility mode control signal, COMPAT, set high, instructs the receivers to follow a different set of rules for the addition and deletion of characters that are non-intrusive to packet data streams, but still enable the device to maintain synchronization between the clock domains. See Section 5.4 for more information. A sufficient number of Idles must be transmitted to guard against overrun. The frequency of Idles can be computed based upon the maximum frequency offset between transmitter and receiver in the system. The number of bytes (characters) that can be transmitted between Idles is: (2*106 / N) - 1 bytes
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Chapter 3. Receiver
3-13
Functional Description
where: N is the frequency offset in ppm. In an underrun situation, data must be added in order to maintain synchronization between the clock domains. If ADIE is high the receiver interface adds a pair of Idle bytes when underrun is imminent. The pair of Idles will be inserted prior to the next pair of Idles in the data stream. This allows the user to establish "packets" of data that do not contain Idles and the MC92602 will NOT insert Idles in the middle of these "packets". The Idle frequency to prevent underruns is identical to the frequency to prevent overruns, so the same conditions apply. If ADIE is disabled and an underrun occurs, the "Underrun" error is reported as described in Section 3.3.6.3 for one byte clock period. The proper phase of the REF_CLK will be provided on RECV_n_CLK. NOTE When operating in "Word" mode all configured channels must add/delete Idles simultaneously. Therefore Idles must appear in the data stream for all channels simultaneously, so that Idles may be inserted (adjacent to existing Idles) or deleted.
3.3.8
Half-Speed Mode
Half Speed mode, Enabled when HSE is asserted high, operates the receiver in its lower speed range. In half speed mode, the link speed is 500 Mbps (625 Mbaud.) The receiver interface operates at half speed as well, in pace with received data.
3.3.9
Repeater Mode
Repeater mode is not recommended for application use. It is used for factory engineering and manufacturing test purposes only. The repeater enable signal, REPE, should be configured low during normal operation.
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Chapter 4 Rate Adaption of Packet Data Streams
This chapter describes how the MC92602 performs rate adaption in applications where the device is used to transmit and receive PCS, PMA, type 1000BASE-X packet streams. When the MC92602 is being operated in reference clock mode, as described in Section 3.3.7, rate adaption is performed to account for frequency offset between the transmitter and receiver. In backplane applications, rate adaption is accommodated by adding K28.5 Idle code groups (characters) to, or deleting K28.5 Idle code groups from, the data stream to match the incoming data rate to the receiver data rate as defined by its reference clock frequency. This indiscriminate addition or deletion of K28.5 Idle characters from an 802.3 packet stream would interfere with proper system operation. NOTE Rate adaption is necessary only if the MC92602 is being operated in the reference clock mode (RCCE = low). The MC92602 compatibility mode, COMPAT, allows for rate adaption using methods compatible with 802.3 packet streams and does not interfere with proper system operation. The following are the features of compatibility mode: * * * * * * * * Context sensitive rate adaption during receipt of configuration, idle and data code groups. Tolerates up to +/- 100 ppm frequency offset. Supports Jumbo frame lengths of up to 16k bytes. Supports frame bursting. Internal or external 8B/10B encoding/decoding may be used. Compatible with specification of Media Access Control function. Compatible with 36 specification of the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer function. Compatible with specification of the Auto-Negotiation function.
The MC92602's compatibility mode is enabled by asserting the control signal, COMPAT, high.
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Chapter 4. Rate Adaption of Packet Data Streams
4-1
Rate Adaption Method
4.1
Rate Adaption Method
The MC92602 utilizes a FIFO in its receiver to act as an elastic buffer for the receive data interface. The elastic buffer allows for proper operation of the interface in the presence of jitter and frequency offset. However, frequency offset will eventually lead to elastic buffer overrun or underrun. In order to prevent underrun and overrun, one or more code groups must be added to or deleted from the packet stream. The MC92602 must determine the proper type of code groups to add or delete and do it at an appropriate time to ensure compatibility with packet data streams. The code group type and timing is determined by the current context of the packet stream. There are three contexts considered: configuration, idle and data transmission.
4.1.1
Configuration Context
The configuration context is when the transceivers are transmitting configuration ordered sets typically in support of auto-negotiation. A configuration ordered set consists of alternating /C1/ and /C2/ code group sets as shown below: /C1/: /K28.5/D21.5/Dxx.x/Dxx.x /C2/: /K28.5/D2.2/Dxx.x/Dxx.x where /Dxx.x/Dxx.x/ represent the 16-bit contents of the configuration register. During auto-negotiation only alternating /C1/ and /C2/ code group sets are expected and the duration of the auto-negotiation sequence is not bounded. Therefore, rate adaption is accomplished through the addition and deletion of /C1/ and /C2/ code group sets. The MC92602, upon detection of an imminent overflow, searches for and deletes two /C1/C2/ code group sets, removing a total of 16 code groups (characters) from the packet stream. The auto-negotiation function is tolerant of missing two complete sets because of its handshaking protocol. Two complete /C1/C2/ code groups sets must be deleted, because, for a constant configuration register value, a single /C1/C2/ code group set toggles running disparity. Removing two /C1/C2/ code group sets maintains proper running disparity. Upon detection of an imminent underflow, the MC92602 searches for two adjacent /C1/C2/ code group sets with a constant configuration register value and inserts a copy of them into the packet stream, adding a total of 16 code groups. The auto-negotiation function is tolerant of additional, valid, sets because of its handshaking protocol. In order to maintain proper running disparity as described above, two complete /C1/C2/ code group sets must be added to the packet stream.
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4.1.2
Idle Context
The idle context is when the transceivers are transmitting idle ordered sets when the link is idle or during inter-packet gaps (IPG). An idle ordered set consists of two types of code group pairs: /I1/: /K28.5/D5.6 /I2/: /K28.5/D16.2 where /I1/ is a correcting idle and /I2/ is a preserving idle. However, there is a more general definition of an idle ordered set as any pair of code groups where the first code group is a /K28.5/ followed by a /Dxx.x/ code group where /Dxx.x/ is not /D21.5/ or /D2.2/. The rules for the insertion of idle ordered sets into a packet stream dictate that the resulting running disparity be negative after the idle code group is inserted. A correcting idle, /I1/, toggles positive running disparity to negative; a preserving idle, /I2/, maintains negative running disparity. These rules are in place specifically to allow the addition or deletion of preserving idle ordered sets by repeaters to accommodate retiming. Therefore, rate adaption in the idle context is accomplished through the addition and deletion of preserving idle ordered sets. The MC92602, upon detection of an imminent overflow, searches for and deletes an /I2/ ordered set, removing a total of two code groups from the packet stream. The packet stream tolerates deletion of /I2/ as described above. Deleting /I2/ raises concerns about IPG shrinkage. The IEEE Std 802.3 specification [5], clause 4.4.2.4, requires the IPG on transmit to be at least 12 code groups in duration, including the end of packet delimiter (EPD). The received IPG is only required to be at least 8 code groups in duration, leaving 4 code groups available to remove per IPG. NOTE The MC92602 does not verify that the IPG meets minimum length requirements after removal of the /I2/ code groups. It assumes that the IPG is at least 12 code groups in length when received. Upon detection of an imminent underflow, the MC92602 searches for an /I2/ ordered set and inserts an /I2/ adjacent to it into the packet stream, adding a total of 2 code groups. The packet stream tolerates additional /I2/ ordered sets because maximum IPG length is not limited. Special consideration is given to IPG in the data context to accommodate Jumbo frames and frame bursting. These are described in the next section.
4.1.3
Data Context
The data context is when the transceivers are transmitting MAC frames encapsulated into code group packets. The code groups in the packet can not be disturbed, therefore, rate
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Chapter 4. Rate Adaption of Packet Data Streams
4-3
Error Handling
adaption is accomplished in the IPG as described above. There are two special cases that must be considered in the data context: Jumbo frames and frame busting. Jumbo frames are not supported in the real standard, but are rather a de facto standard. Jumbo frames violate the untagged maximum frame size of 1518 code groups and increases the size to 16k code groups. Given a maximum total frequency offset of 200 ppm and the size of the MC92602's elastic buffers, a Jumbo frame could lead to a surplus or deficit of 3.3 code groups for which rate adaption must account. The MC92602, upon detection of an imminent overflow, searches for and deletes an /I2/ ordered set, removing a total of two code groups from the IPG. If a Jumbo frame is detected by evidence of a large surplus, two /I2/ ordered sets are deleted, removing a total of four code groups. Similarly, upon detection of an imminent underflow, the MC92602 searches for a /I2/ ordered set and inserts an /I2/ adjacent to it into the IPG, adding a total of two code groups. If a Jumbo frame is detected by evidence of a large deficit, two /I2/ ordered sets are inserted, adding a total of four code groups. The size of the elastic buffers are increased by 8 to accommodate accumulation of four code groups to guard against later deficit, and to allow for the accumulation of an additional four surplus code groups. In half-duplex mode of operation as defined by the standard, frame bursting is allowed. Frame bursting is an artifact of the CSMA/CD media access mechanism where idle ordered sets in the IPG are used to signal availability of the medium. Frame bursting allows the transmitter to retain ownership of the medium by inserting carrier extend, /R/, ordered sets in the IPG in place of idle ordered sets. A frame burst can be as long as 65k bits (8k code groups). An idle-based IPG must exist between frame bursts. Frame bursts are shorter than Jumbo frames, therefore, frame bursting is supported using the same mechanism as Jumbo frames just described.
4.2
Error Handling
The receiver interface error reporting mechanisms as described in Section 3.3.6.3 are used in compatibility mode with one exception; overrun/underrun errors are processed differently. Overrun may occur when an appropriate code group to remove can not be identified. In this situation, one data code group is removed from the packet stream. The received packet stream continues normally thereafter. The code group immediately following the removed code group is reported as an overrun error as described in Section 3.3.6.3. The MAC sublayer should detect the missing code group as a CRC error. Underrun may occur when an appropriate code group to insert can not be identified. In this situation, one data code group is repeated in the packet stream. The received packet stream
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Special Considerations
continues normally thereafter. The repeated code group is reported as an underrun error as described in Section 3.3.6.3. The MAC sublayer should detect the repeated code group as a CRC error.
4.3
Special Considerations
When the compatibility mode is enabled by setting COMPAT high, special rules for rate adaption are followed as described above. Additionally, the receiver's elastic buffers operate differently to account for Jumbo frames. In order to ensure against starvation of the elastic buffer in the presence of Jumbo frames, the elastic buffers are allowed to accumulate four additional code groups, leading to longer receiver latency. Receiver latency increases by four code groups, 40 bit-times, when in the compatibility mode. Word synchronization, as described in Section 3.3.4, is not supported in the compatibility mode. Each channel is considered to be an independent packet stream. If the MC92602 is being operated in recovered clock mode, see Section 3.3.7.1, then rate adaption is not performed by the device and the data stream is transferred unmodified. The compatibility mode would have no effect on device operation and is not required. The compatibility mode should not be used in backplane applications that are not utilizing standard protocol.
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Special Considerations
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Chapter 5 System Design Considerations
This chapter describes general system considerations for the MC92602 Quad DDR, including device-startup, initialization and the proper use of the configuration and control signals, the reference clock configuration, and general recommendations.
5.1
Reference Clock Configuration
The clock inputs REF_CLK_P and REF_CLK_N are the differential reference clock inputs for the MC92602. The frequency of the clock signal applied to these inputs along with the settings on the configuration inputs determine the speed at which the serial links operate. Also, the legal ranges of reference clock frequencies vary depending on the configuration selected. Table 5-1 shows the ranges allowed for each configuration.
Table 5-1. Legal Reference Clock Frequency Ranges
HSE Low High Reference Frequency Min (MHz) 95.00 47.50 Reference Frequency Max (MHz) 135.0 67.50 Link Transfer Rate (Gigabaud) 0.95 - 1.35 0.475 - 0.675
NOTE The device must be reset by setting RESET low, if the reference clock configuration, HSE, is changed after power-up. The clock inputs REF_CLK_P and REF_CLK_N are normally driven with a differential clock source. However, the reference clock may also be driven with a single-ended source. In this situation, the REF_CLK_P signal is driven by the single-ended clock source and the REF_CLK_N signal is held at the HSTL reference voltage as defined in Section 5.8. The REF_CLK_N signal may be connected to its own reference voltage circuit or may share the reference voltage circuit used for the HSTL_VREF signal, if board layout allows.
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5-1
Startup
5.2
Startup
The MC92602 begins a startup sequence upon application of the reference clock (REF_CLK_N/P input) to the device. This is considered a cold startup. The cold startup sequence is as follows: 1. 2. 3. 4. PLL Startup Receiver Initialization and Byte Alignment Word Alignment (if enabled) Run
The expected duration of each step in the startup sequence is shown in Table 5-2. A cold startup can be initiated at any time by setting RESET low. It is recommended that RESET be low at initial startup, however, it is not strictly required.
Table 5-2. Startup Sequence Step Duration
Startup Step PLL Startup Receiver Initialization Typical Duration (in bit times) 10,2400 + 25 s 50 160 Word Alignment 50 160 WSE = low WSE = high WSE = low WSE = high Note
5.3
Standby Mode
Standby mode puts the MC92602 into a low power, inactive state. When STNDBY is asserted high, the device will force all transmitter link outputs to their disabled state as defined in Section 2.3.3, and will disable all internal clocking. An important feature of standby mode is that the internal PLL is not disabled. It remains operating and locked to the reference clock. This greatly reduces the time needed to recover from standby mode to run mode, as only the receiver initialization and word alignment startup steps are required.
5.4
Configuration and Control Signals
The MC92602 has many configuration and control signals that are asynchronous to all inputs clocks. Most of the signals affect the internal configuration state and must be set at power-up. If their state is changed after power-up, some require that the chip be reset by setting RESET low and then releasing high. While other configuration signals are meant to be changed during normal operation and do not require chip reset. However, these signals may still affect device operation. Table 5-3 lists all of the MC92602's asynchronous
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Power Supply Requirements
configuration and control signals and describes the effect of changing their state after power up.
Table 5-3. Asynchronous Configuration and Control Signals
Signal Name XCVR_x_DISABLE Description Transceiver Disable Effect of Changed State Receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. Receiver must re-establish byte and word synchronization. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Must be low and remain low during normal operation. Device must be reset. Device must be reset. Must be low and remain low during normal operation. Receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. Enable/disable transmit links during testing (LBOE = high), no recovery action necessary. Receiver must re-establish byte and word synchronization. Device is reset.
DROP_SYNC XMIT_REF_A RECV_REF_A TBIE HSE BSYNC ADIE COMPAT REPE RCCE WSE TST_0, TST_1 LBE
Drop Synchronization Transmitter Reference Clock A Select Receiver Reference Clock A Select Ten-Bit Interface Enable Half-Speed Enable Byte Synchronization Mode Add/Drop Idle Enable Compatibility Mode Repeater Mode Enable Recovered Clock Enable Word Synchronization Enable Test Mode Identifiers Loop Back Enable
LBOE STNDBY RESET
Loop Back Output Enable Puts PLL in Standby Mode System Reset Bar
5.5
Power Supply Requirements
The recommended board for the MC92602 has a minimum of two solid planes of one ounce copper. One plane is to be used as a ground plane and the second plane is to be used for the 1.8V supply. It is recommended that the board has its own 1.8V and 1.5V regulators with less than 50mV ripple.
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5-3
Phase Locked Loop (PLL) Power Supply Filtering
5.6
Phase Locked Loop (PLL) Power Supply Filtering
An analog power supply is required. The PLLAVDD signal provides power for the analog portions of the PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 5-1. For maximum effectiveness, the filter circuit is placed as close as possible to the PLLAVDD ball to ensure it filters out as much noise as possible. The ground connection should be near the PLLAGND ball. The 0.01F capacitor is closest to the ball, followed by the 1 F capacitor, and finally the 1 resistor to Vdd on the 1.8V power plane. The capacitors are connected from PLLAGND to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct.
1 VDD 1.0 F 0.01 F PLLAVDD
GND
Figure 5-1. PLL Power Supply Filter Circuits
5.7
Power Supply Decoupling Recommendations
The MC92602 requires a clean, tightly regulated source of power to ensure low jitter on transmit, and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used, to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. First, the board should have about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 1.8v (Vdd and XVdd) balls of the device. The board should also have about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 1.5v (VDDQ) balls of the device. Where the board has blind vias, these capacitors should be placed directly below the MC92602 supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the MC92602, as close to the supply and ground connections as possible. Second, there should be a 1uF ceramic chip capacitor on each side of the MC92602 device. This should be done for both the 1.8v supply and the 1.5v supply. Third, between the MC92602 device and the voltage regulator, there should be a 10uF, low equivalent series resistance (ESR) SMT tantalum chip capacitor, and a 100uF, low ESR
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HSTL Reference Voltage Recommendation
SMT tantalum chip capacitor. This should be done for both the 1.8v supply and the 1.5v supply.
5.8
HSTL Reference Voltage Recommendation
The MC92602 uses HSTL Class-I inputs and outputs for all of its high-frequency parallel interface signals. The HSTL Class-I interfaces are compatible with the EIA/JEDEC standard EIA/JESD8-6 [3]. HSTL Class-I inputs define their switching thresholds about a reference voltage supplied at an input of the device. The reference voltage is applied to the HSTL_VREF input of the MC92602. The reference voltage, referred to as VREF in Table 7-3, must fall within the minimum and maximum voltages as specified and must have no more than 2 percent peak-to-peak AC noise. In practice, VREF for the HSTL inputs should track the variations in the DC value of VDDQ of the sending device for best noise margin. The value of VREF is to be selected by the user to provide optimum noise margin. Figure 5-2 shows a recommended circuit topology to generate VREF with recommended ceramic chip filter capacitor.
VDDQ
100 HSTL_VREF 110 1.0 F
GND
GND
Figure 5-2. HSTL Class-I VREF Circuit
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Chapter 5. System Design Considerations
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HSTL Reference Voltage Recommendation
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Chapter 6 Test Features
The MC92602, supports several test modes for Built In System Test, BIST, and production testing. The MC92602 also has an IEEE Std. 1149.1 [4] compliant Test Access Port and Boundary Scan Architecture implementations. This chapter covers the JTAG implementation and the system accessible test modes.
6.1
IEEE Std. 1149.1 Implementation
This section describes the IEEE Std. 1149.1 compliant Test Access Port and Boundary Scan Architecture implementation in the MC92602.
6.1.1
Test Access Port (TAP) Interface Signals
Table 6-1. TAP Interface Signals
Table 6-1 lists the interface signals for the TAP.
Signal Name TCK TMS TDI TRST TDO
Description Test Clock Test Mode Select Test Data In Test Reset Bar Test Data Out
Function Test logic clock. TAP mode control input. Serial test instruction/data input. Asynchronous test controller reset. Serial test instruction/data output.
Direction Input Input Input Input Output
Active State Low -
NOTE There are 10K Ohm pull-ups on the TMS, TDI and TRST. If TRST is not held low during power-up or does not receive an active low reset after power-up, the test logic may assume an indeterminate state disabling some of the normal transceiver functions. It is recommended that TRST be terminated in one of the following ways: 1. TRST be driven by a TAP controller that provides a reset after power-up.
MOTOROLA Chapter 6. Test Features 6-1
IEEE Std. 1149.1 Implementation
2. Connect TRST to RESET. 3. Terminate TRST with a 1K Ohm resistor (or hard wire) to ground.
6.1.2
Is the
Instruction Register
Bit Position 3 Field Capture-IR Value 0 0
2 1 0
IR 0 1
Figure 6-1. Instruction Register
6.1.3
Instructions
Table 6-2 lists the public instructions provided in the implementation and their instruction codes.
Table 6-2. Tap Controller Public Instructions
Instruction BYPASS CLAMP EXTEST HIGHZ IDCODE SAMPLE Code 1111 1100 0000 1001 0001 0010 Bypass Register Bypass Register Boundary Scan Register Bypass Register ID Register Boundary Scan Register Enabled Serial Test Data Path
Table 6-3 lists the Private instruction codes that if executed could be hazardous to device operation. The user should not execute these instructions.
Table 6-3. Tap Controller Private Instruction Codes
Instruction Code 0011 0100 0101 0110 0111 Instruction Code 1000 1010 1011 1110 -
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6.1.4
Boundary-Scan Register
A full description of the boundary scan register may be found in the BSDL file provided by Motorola upon request.
6.1.5
Device Identification Register (0x0281601D)
28 27 12 11 0
Bit Position 31
Field VERSION
PART NUMBER
MANUFACTURER ID
Value 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1
Figure 6-2. Device Identification Register
6.1.6
Performance
The performance and electrical properties of the tap controller, boundary scan, and JTAG inputs and outputs are described in Chapter 7, "Electrical Specifications and Characteristics.
6.2
System Accessible Test Modes
System accessible test modes are selected through the TST_0, TST_1 and LBE signals. Table 6-4 shows test mode state selection.
.
Table 6-4. Test Mode State Selection
TST_1 Low Low Low Low High High High High TST_0 Low Low High High Low Low High High LBE Low High Low High Low High Low High Description Normal operation. No test mode enabled. Loop back system test mode. BIST sequence system test mode with IDLEs inserted for rate adaption. Loop back BIST sequence system test mode. BIST sequence system test mode without IDLEs inserted for rate adaption. Reserved. Reserved. Reserved.
6.2.1
Loop Back System Test
The MC92602 can be configured in loop back mode where the transmitted data is looped back to its receiver independent of the receiver's link inputs. This is enabled by setting Loop Back Enable, LBE, high. The characters transmitted are controlled by the normal transmitter controls. If the transceiver is working properly, the data/control characters
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Chapter 6. Test Features
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System Accessible Test Modes
transmitted are received by the receiver. This allows system logic to use various data sequences to test the operation of the transceiver. The loop-back signals are electrically isolated from the XLINK_x_P or XLINK_x_N output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. When in loop-back mode, the loop-back output enable, LBOE, signal controls the action of the link output signals. When LBOE is low, the XLINK_x_P or XLINK_x_N output signals are disabled and are high-impedance. When LBOE is high, the link output signals continue to operate normally. The receiver's link input signals, RLINK_x_P and RLINK_x_N, are electrically isolated during loop back mode, such that their state does not affect the loop back path.
6.2.2
BIST Sequence System Test Mode
The MC92602's transmitter has an integrated, 23rd order, Pseudo-Noise (PN) pattern generator. Stimulus from this generator may be used for system testing. The receiver, has a 23rd order signature analyzer that is synchronized to the incoming PN stream and may be used to count character mismatch errors relative to the internal PN reference pattern. This implementation of the 23-bit PN generator and analyzer uses the polynomial: f = 1 + x5 + x23 The total mismatch error count is reset to zero when BIST mode is entered. The count is updated continuously while in BIST mode. The value of the count is presented on the receiver interface signals: RECV_x_3 through RECV_x_0 (as interpreted and shown in Table 3-4), making up the eight-bit error count, ordered bits 7 through 0, respectively. The value of the count is sticky in that the count will not wrap to zero upon overflow, but rather, stays at the maximum count value (11111111). The RECV_x_ERR, RECV_x_K (as interpreted and shown in Table 6-5), have special meaning during this test mode. They report the status of the receiver and PN analysis logic. Table 6-5 describes the BIST error codes and their meaning. E0 and K0 are the values on RECV_x_ERR and RECV_x_K, respectively, on the rising edge of the recovered clock. E1 and K1 are the values of RECV_x_ERR and RECV_x_K, respectively, on the falling edge of the recovered clock
.
Table 6-5. BIST Error Codes
E0 Low Low Low E1 Low High High K0 Don't care Low Low K1 Description
Don't care BIST running, no PN mismatch this character. Low High BIST running, PN mismatch error this character. Receiver byte/word synchronized, PN analyzer is not locked.
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System Accessible Test Modes
Table 6-5. BIST Error Codes
High High Low High Don't care Don't care Don't care Not Byte Sync: The receiver is in start-up or has lost byte alignment and is searching for alignment. Don't care Not Word Sync: The receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment.
The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode overrides the setting on TBIE signal and forces Byte Interface mode. Additionally, the BIST sequence requires that a normal byte alignment mode be used. The setting of BSYNC is overridden, forcing the device into the Byte Aligned mode (forces BSYNC high internally). BIST is run at the speed indicated by the frequency of the reference clock and by the speed range selected by half-speed mode (HSE). The settings of WSE, RCCE, RECV_REF_A are not altered and BIST will follow their setting. In order to properly use this test mode, the system must provide the proper stimulus in a special sequence. The sequence is as follows: Step 1: Enter test mode by setting the test mode inputs as described in Table 6-4. Step 2: Transmit 4096 IDLEs (K28.5 characters). Step 3: Transmit to the receiver an 8B/10B encoded PN sequence as described above. The transmitter will automatically go through steps 2 and 3 upon entering this test mode. When testing is complete, the device will need to be reset before normal operation can resume. There are two test configurations for BIST as defined in Table 6-4. One operates as just described above. The second mode, (TST_1 = low, TST_0 = high, LBE = low), inserts 2 IDLES every 2048 characters during step 3. The signature analyzers ignore the Idle character. NOTE The receiver signature analyzers assume all four channels are being exercised. If BIST testing is being performed between devices, or by means of external loop back on selected channels, the unused channel receivers must be disabled or the analyzers will not go into the PN Sync state. That is, receivers not having an PN stimulus must have XCVR_x_DISABLE asserted.
MOTOROLA
Chapter 6. Test Features
6-5
Loop-Back BIST Sequence System Test Mode
6.3
Loop-Back BIST Sequence System Test Mode
The test mode is the combination of the Loop-Back and BIST Sequence System Test Modes. The device operates as described in Section 6.2.1 and Section 6.2.2. However, the need to go through the startup sequence is eliminated because the transmitter automatically goes through the proper sequence.
6-6
MC92602 SERDES Reference Manual
MOTOROLA
Chapter 7 Electrical Specifications and Characteristics
This chapter explains the electrical specifications and characteristics of the MC92602 device. This chapter consists of the following sections: * * * Section 7.1, "General Characteristics," Section 7.2, "DC Electrical Specifications," and Section 7.3, "AC Electrical Characteristics."
7.1
General Characteristics
This section presents the general technical parameters, the maximum and recommended operating conditions for the MC92602.
7.1.1
* * * * *
General Parameters
Technology--0.25 lithography, HiP4 CMOS, 5 layer metal Package--196 MAPBGA, 15x15 mm Body Size, 1mm Ball Pitch Core Power Supply--1.8V + 0.15V dc HSTL I/O Power Supply--1.5V + 0.1 V dc or 1.8V + 0.15V dc Link I/O Power Supply--1.8V + 0.15
The following provides a summary of the general parameters of the MC92602:
MOTOROLA
Chapter 7. Electrical Specifications and Characteristics
7-1
General Characteristics
7.1.2
Absolute Maximum Rating
Table 7-1, in this section, describes the MC92602's, absolute maximum DC electrical ratings.
Table 7-1. Absolute Maximum Ratings
Characteristics 1 Core Supply Voltage PLL Supply Voltage HSTL I/O Supply Voltage Link I/O Supply Voltage HSTL Input Voltage CMOS Input Voltage Link Input Voltage Storage Temperature Range ESD Tolerance Symbol VDD AVDD VDDQ XVDD Vin Vin Vin Tstg HBM MM
1
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 2,000 200
Max 2.2 2.2 2.2 2.2 VDDQ + 0.3 VDD + 0.3 XVDD + 0.3 150 -
Unit V V V V V V V
oC
V V
Functional and tested operating conditions are given in Table 7-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums are not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
7.1.3
Recommended Operating Conditions
Table 7-2 in this section describes the recommended operating conditions for the MC92602.
Table 7-2. Recommended Operating Conditions
Characteristic 1, 2 Core Supply Voltage PLL Supply Voltage HSTL I/O Supply Voltage (1.5V Operation) HSTL I/O Supply Voltage (1.8V Operation) Link I/O Supply Voltage HSTL Input Voltage CMOS Input Voltage Link Input Voltage Symbol VDD AVDD VDDQ VDDQ XVDD Vin Vin Vin Min 1.65 1.65 1.40 1.65 1.65 0 0 0 Max 1.95 1.95 1.60 1.95 1.95 VDDQ VDD XVDD Unit V V V V V V V V
7-2
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MOTOROLA
DC Electrical Specifications
Table 7-2. Recommended Operating Conditions (continued)
Characteristic 1, 2 Junction Temperature Ambient Temperature 3
1
Symbol Tj Ta
Min -40 -
Max 105 -
Unit
oC oC
These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2 Recommended supply power-up order is V , AV , V DD DD DDQ, XVDD, however, any order is acceptable as long as Maximum Ratings are not exceeded. 3 Operating Ambient Temperature is dependent on proper thermal management to meet operating Junction Temperature
7.2
DC Electrical Specifications
Table 7-3. DC Electrical Specifications
Characteristic 1 Symbol IDD AIDD IDDQ XIDD PD VREF VIH DC VIL DC VIH AC VIL AC IIH IIL VOH VOL Cin Rout VIH VIL Min -- -- -- -- -- 0.68 VREF + 0.1 VREF + 0.2 VDDQ - 0.4 35 1.0 Max 650 10 108 47 -- 0.9 -- VREF - 0.1 VREF - 0.2 80 275 0.4 8 55 0.5 Unit mA mA mA mA mW V V V V V A A V V pF V V
Table 7-3 in this section describes the MC92602 DC electrical characteristics.
Core Supply Current 2 PLL Supply Current 2 HSTL I/O Supply Current 2 Link I/O Supply Current 2 Total Power Dissipation 3 HSTL Reference Voltage HSTL Input High Voltage (DC) HSTL Input Low Voltage (DC) HSTL Input High Voltage (AC) HSTL Input Low Voltage (AC) HSTL Input Leakage Current, Vin = VDDQ HSTL Input Leakage Current, Vin = GND HSTL Output High Voltage HSTL Output Low Voltage HSTL Input Capacitance HSTL Output Impedance, Vout = VDDQ/2 CMOS Input High Voltage CMOS Input Low Voltage
MOTOROLA
Chapter 7. Electrical Specifications and Characteristics
7-3
AC Electrical Characteristics
Table 7-3. DC Electrical Specifications (continued)
Characteristic 1 CMOS Input Leakage Current, Vin = VDDQ CMOS Input Leakage Current, Vin = GND CMOS Input Capacitance Link Common Mode Input Impedance Link Differential Input Impedance (MEDIA = low/high) Link Common Mode Input Level 4 Link Differential Input Amplitude Link Input Capacitance Link Common Mode Output Level Link Differential Output Amplitude, (100/150 diff load, MEDIA = low/high) Link Differential Output Impedance (MEDIA = low/high) typical
1 2
Symbol IIH IIL Cin Rcm Rdiff Vcm Vin Cin Vcm Vout Rout
Min 2 85/127.5 0.725 0.4 0.725 1.3
Max 10 10 10 4 130/195 1.225 3.2 3 1.075 2.2
Unit A A pF k V Vp-p pF V Vp-p
100/150 5
VDD = AVDD = XVDD = 1.8 + 0.15 V dc, VDDQ = 1.5 + 0.1 V dc, GND = 0 V dc, -40 < Tj < 105C. Currents maximums at VDD = AVDD = XVDD = VDDQ =1.95 V dc, all links operating at full-speed. 3 Typical P (mWatts) = 95.4 + 37.8n + 0.3nf + 6.4f; where n = number of active channels and f = Reference frequency D in MHz. 4 Subject to absolute voltage on link input pin remaining in recommended range per Table 7-2. 5 Typical values
7.3
AC Electrical Characteristics
The figures and tables in this section describe the AC electrical characteristics of MC92602. All specifications stated are for Tj = -40C to 105C, VDD = AVDD = XVDD = 1.65V to 1.95V, VDDQ = 1.4V to 1.6V
7.3.1
.
Parallel Port Interface Timing
XMIT_x_CLK XMIT_x_3-0 XMIT_x_K T1
bits 3-0
bits 7-4
bits 3-0
bits 7-4
T2
T1
T2
Figure 7-1. Transmitter DDR Interface Timing Diagram
7-4
MC92602 SERDES Reference Manual
MOTOROLA
AC Electrical Characteristics
Table 7-4. Transmitter DDR Timing Specification
Symbol T1 T2 Characteristic Setup time to rising/falling edge of XMIT_x_CLK Hold time to rising/falling edge of XMIT_x_CLK Min 0 0.960 1.3 2 drift Phase drift between XMIT_x_CLK and REF_CLK_P -180 180
1
Max -
Unit ns ns ns degrees
1 Synchronous to channel's transmit interface clock, XMIT_REF_A=Low. 2 Synchronous to XMIT_A_CLK, XMIT_REF_A = High.
..
RECV_x_CLK RECV_x_3-0 RECV_x_K RECV_x_ERR
bits 3-0
bits 7-4
bits 3-0
bits 7-4
T1
T2
T1
T2
Figure 7-2. Receiver Interface DDR Timing Diagram Table 7-5. Receiver DDR Timing Specification
Symbol T1 Characteristic Output valid time before rising/falling edge of RECV_x_CLK Output valid time after rising/falling edge of RECV_x_CLK Min 1.3 1 1.3 2 1.3
1
Max 1.0 1.0
Unit ns ns ns ns ns ns
T2
5.3 2 Tf Tr
1 2
Output fall
time 3
-
Output rise time 3
Full speed, 125MHz operation (HSE = low). Half-speed, 62.5MHz operation (HSE = high). 3 10pF output load.
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Chapter 7. Electrical Specifications and Characteristics
7-5
AC Electrical Characteristics
7.3.2
Reference Clock Timing
REF_CLK_N REF_CLK_P Tf, Tr 1/frange Tdiff
Figure 7-3. Reference Clock Timing Diagram Table 7-6. Reference Clock Specification
Symbol Tr Tf frange frange TD Tdiff ftol Tj Tlock
1 2 3 4 5 6
Characteristic REF_CLK_P/N rise time 1 REF_CLK_P/N fall time 1 REF_CLK_P/N frequency range 2, 3 REF_CLK_P/N frequency range 2, 4 REF_CLK_P/N duty cycle REF_CLK_P to REF_CLK_N differential skew REF_CLK_P/N frequency tolerance REF_CLK_P/N input jitter 5 PLL lock time 6
Min 95 47.5 45 -200 -
Max 2.0 2.0 135 67.5 55 1.0 200 80
Unit ns ns MHz MHz Percent ns ppm ps
20,480 + bit-times 25 s
Measured between 10-90 percent points. Measured between 50-50 percent points. Full speed operation (HSE = low). Half speed operation (HSE = high). Total peak-to-peak jitter. Lock time after compliant REF_CLK_P/N signal applied.
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AC Electrical Characteristics
7.3.3
Receiver Recovered Clock Timing
RECV_x_CLK
Trck
Tsrck Tf, Tr
Tlrck
Figure 7-4. Recovered Clock Timing Diagram Table 7-7. Recovered Clock Specification
Symbol Trck Characteristic RECV_x_CLK period (normal cycle) 1, 2 Min 8.0 3 16.0 4 Tsrck RECV_x_CLK period (short cycle) 1, 2 7.8 3 15.6 Tlrck RECV_x_CLK period (long cycle) 1, 2
4
Max -
Unit ns ns ns ns ns ns
8.2 3 16.4
4
Tr Tf TD Tj
RECV_x_CLK rise time 5 RECV_x_CLK fall time
5
45 -
1.0 1.0 55 200 3 400 4
ns ns % ps ps
RECV_x_CLK duty cycle RECV_x_CLK jitter 6
1 2 3 4 5 6
Measured between 50-50 percent points, 125MHz REF_CLK. Includes jitter component. Normal speed Half speed Measured between 10-90 percent points. Total peak-to-peak jitter.
MOTOROLA
Chapter 7. Electrical Specifications and Characteristics
7-7
AC Electrical Characteristics
7.3.4
Serial Data Link Timing
XLINK0/1_x_P XLINK0/1_x_N Tj Tds
Figure 7-5. Link Differential Output Timing Diagram Table 7-8. Link Differential Output Specification
Symbol Tj Tdj Tds Xla t
1 2
Characteristic Total jitter 1 Deterministic jitter Differential skew 1 Transmit latency
2 1
Min -
Max 0.24 0.12 25 67
Unit UI UI ps bit-times
Measured between 50-50 percent points. Rising edge REF_CLK_P to bit 0 transmit.
RLINK0/1_x_P RLINK0/1_x_N Tjtol Tdstol
Figure 7-6. Link Differential Input Timing Diagram Table 7-9. Link Differential Input Timing Specification
Symbol Tr Tf Tjtol Tdjtol Tdstol Rlat Tacq
1 2
Characteristic Link input rise time 1 Link input fall time 1
Min 300 300 0.71 0.45 175 -
Max
Unit ps ps
Total jitter tolerance 2 , 3 Deterministic jitter tolerance 2, 3
190 300 5
UI UI ps bit-times bit-times
Differential skew tolerance 2, 3 Receive latency 4
Receiver phase acquisition time
Measured between 10-90 percent points Measured between 50-50 percent points, 125 MHz REF_CLK, 1.25 Gbaud 3 Per IEEE 802.3z specification
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AC Electrical Characteristics
4 5
Bit 0 at receiver input to parallel data out Measured with worst-case eye opening, Idle pattern, and reference PLL locked.
7.3.5
JTAG Test Port Timing
TCK
1/fTCK
TDO T1 TDI TMS T2 T3
Figure 7-7. JTAG I/O Timing Diagram Table 7-10. JTAG I/O Timing Specification
Symbol T1 T2 T3 fTCK TD
1
Characteristic Output propagation time after falling edge of TCK 1 Setup time to rising edge of TCK Hold time to rising edge of TCK TCK frequency TCK duty cycle
Min 1.0 1.0 0.5 35
Max 8.0 20 65
Unit ns ns ns MHz Percent
10 pF output load
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Chapter 7. Electrical Specifications and Characteristics
7-9
AC Electrical Characteristics
7-10
MC92602 SERDES Reference Manual
MOTOROLA
Chapter 8 Package Description
The following section provides the package parameters and mechanical dimensions of the MC92602 device. The MC92602 is offered in a 196 MAPBGA package. The 196 MAPBGA utilizes an aggressive 1 mm ball pitch and 15 mm body size for application where board space is limited.
8.1
* * * * * *
196 MAPBGA Package Parameter Summary
Package Type--Fine pitch ball grid array Package Outline--15 mm x 15 mm Package Height--1.60 mm Max Number of Balls--196 Ball Pitch--1 mm Ball Diameter--0.45-0.55 mm
8.2
Nomenclature and Dimensions of the 196 MAPBGA Package
Figure 8-1 provides the bottom surface nomenclature and package outline drawing of the 196 MAPBGA package. Figure 8-2 provides the package dimensions. Figure 8-3 provides a graphic of the package pin signal mappings.
MOTOROLA
Chapter 8. Package Description
8-1
Nomenclature and Dimensions of the 196 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT 1998 MOTOROLA. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING D
98ARH98217A PAGE ISSUE O 1128C DATE 28JUL98
X Y
LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
M
(SHEET 2 OF 2)
DETAIL K
E
4X 0.15
TOP VIEW 13X e S
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D
M
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
13X e
E F G H J K L M N P
S
BOTTOM VIEW
196X
b 0.15 M 0.08 M
3 ZXY Z
VIEW M-M
TITLE CASE NUMBER: STANDARD: REFERENCE:
196 I/O STD MAP BGA, 15 X 15 PKG, 1.00 PITCH
1128C-01 SHEET 1 OF 2
MOTOROLA U, X
Figure 8-1. 196 MAPBGA Nomenclature
8-2
MC92602 SERDES Reference Manual
MOTOROLA
Nomenclature and Dimensions of the 196 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT 1998 MOTOROLA. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING
98ARH98217A PAGE ISSUE O 1128C DATE 28JUL98
5 0.20 A2 Z
A
196X
A1 Z 4 0.10 Z
DETAIL K
VIEW ROTATED 90 CLOCKWISE
DIM
MIN
MAX
NOTES
A A1 A2 b D E e S
1.25 0.27 1.16 REF 0.45 15.00 BSC 15.00 BSC 1.00 BSC
1.60 0.47
1 2
3
DIMENSIONS ARE IN MILLIMETERS. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL
0.55
4 5
TITLE
196 I/O STD MAP BGA 15 X 15 PKG, 1.00 PITCH
CASE NUMBER: STANDARD: REFERENCE:
1128C-01 SHEET 2 OF 2
MOTOROLA U, X
Figure 8-2. 196 MAPBGA Dimensions
MOTOROLA
Chapter 8. Package Description
8-3
Nomenclature and Dimensions of the 196 MAPBGA Package
.
14 13 12
HSE
11
RESET_B
10
XMIT_ D_7
9
XMIT_ D_5 XMIT_ D_6
8
XMIT_ D_2 XMIT_ D_3
7
XMIT_ C_0 XMIT_ C_1 XMIT_ C_3 XMIT_ C_2
6
XMIT_ C_4 XMIT_ C_5 XMIT_ C_K XMIT_ C_7
5
XMIT_ C_6
4
RECV_ D_ERR
3
RECV_ D_RCLK
2
RECV_ D_K
1
RECV_ D_4
XPADGND REPE RLINK_ XPADVDD D_N
A B C D E F G H J K L M N P
WSE
REF_CLK XMIT_ D_K
ADIE
RECV_ RECV_ XMIT_C_ PADV DD D_9 PADV DD D_2 IDLE_B RECV_ D_5 RECV_ D_7 RECV_ C_2 RECV_ D_6 RECV_ D_0 RECV_ C_4 RECV_ C_9 RECV_ D_3 RECV_ C_0
RLINK_ XPADGND RCCE D_P
STNDBY PADV DD XMIT_ D_1
XMIT_ D_4 XMIT_ D_0
XPADGND XPADVDD XLINK_ XPADVDD DDRE D_N RLINK_ XPADV XLINK_ DD D_P C_P
RECV_ D_IDLE
RECV_ PADV DD C_1 RECV_ C_3 RECV_ C_7 RECV_ C_6 RECV_ C_K
RECV_ XLINK_ XMIT_D_ COREGND/ COREGND/ COREV COREV COREVDD DD DD D_1 C_P IDLE_B PADGND PADGND
RECV_ RLINK_ XLINK_ XPADVDD XPADGND COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREVDD PADGND PADGND PADGND PADGND C_5 C_N C_N
XPADGND PLLAGND XPADVDD XPADGND COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREVDD PADV DD RECV_ B_IDLE PADGND PADGND PADGND PADGND RECV_ RLINK_ PLLAVDD PLL_TPA XPADGND COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREVDD B_RCLK B_N PADGND PADGND PADGND PADGND
RECV_ RLINK_ XLINK_ COREV COREGND/ COREGND/ COREGND/ COREGND/ COREV XPADVDD XPADGND DD B_K DD PADGND PADGND PADGND PADGND B_P B_N RECV_ B_7
RECV_ C_IDLE RECV_ B_ERR
RECV_ C_RCLK RECV_ C_ERR
RECV_ RECV_ PADV DD B_3 B_9 RECV_ B_0 RECV_ B_5 RECV_ B_6
XPADGND XPADVDD XLINK_ A_P
RECV_ XLINK_ COREV DD COREVDD COREVDD COREVDD COREVDD COREVDD B_4 B_P XMIT_ A_4 XMIT_ A_0 XMIT_ B_2 XMIT_ B_3 XMIT_ B_1 XMIT_ B_0 XMIT_ B_7 XMIT_ B_K XMIT_ B_5 XMIT_ B_4
RLINK_ XPADVDD XLINK_ XPADGND TST_1 A_P A_N
RECV_ A_IDLE
RECV_ A_5
RECV_ RECV_ PADV DD PADV DD B_2 B_1 RECV_ A_7 RECV_ A_6 RECV_ A_2 RECV_ A_3 RECV_ A_K RECV_ A_0 RECV_ A_1 RECV_ A_4
RLINK_ XPADVDD BSYNC_1 XPADVDD WSE_GEN PADV DD XMIT_ A_N A_1 XPADGND MEDIA
TBIE TST_0 XMIT_ A_K XMIT_ A_7 XMIT_ A_6 XMIT_ A_5 XMIT_ A_3 XMIT_ A_2
RECV_ XMIT_B_ PADV DD A_9 IDLE_B XMIT_ B_6
LBOE
LBE
BSYNC_0 XMIT_A_ IDLE_B
RECV_ A_ERR
RECV_ A_RCLK
View G-G (Bottom View)
Figure 8-3. 196 MAPBGA Package
8-4
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MOTOROLA
Package Thermal Characteristics
8.3 Package Thermal Characteristics
Thermal values for the 196 pin MAPBGA are listed below in Table 8-1. The values listed below assume the customer will be mounting the packages on a thermally enhanced mother board. This is defined as a minimum 4-layer board with one ground plane. The values listed below were measured in accordance with established JEDEC (Joint Electron Device Engineering Council) standards.
Table 8-1. MC92602 Package Option Thermal Resistance Values
Symbol Description Thermal resistance from junction to ambient, still air 196 MAPBGA 38
o
Units
ja-0 ja-2 ja-4
1
CW
Thermal resistance from junction to ambient, 200 LFM 1
34
o
CW
Thermal resistance from junction to ambient, 400 LFM1
33
o
CW
Linear feet per minute
8.4 MC92602 Chip Pinout Listing
The MC92602 is offered in a 196 MAPBGA package. Table 8-2 list the MC92602 signal to ball location mapping for the package. Also shown are signaling direction (input or output), and the type of logic interface.
Table 8-2. 196 Signal to Ball Mapping
Signal Name XMIT_A_0 XMIT_A_1 XMIT_A_2 XMIT_A_3 XMIT_A_4 XMIT_A_5 XMIT_A_6 XMIT_A_7 XMIT_A_K XMIT_A_IDLE Description Transmitter A, data bit 0 Transmitter A, data bit 1 Transmitter A, data bit 2 Transmitter A, data bit 3 Transmitter A, data bit 4 Transmitter A, data bit 5 Transmitter A, data bit 6 Transmitter A, data bit 7 Transmitter A, special character (data bit 8 for TBI mode) Transmitter A, idle enable bar, (data bit 9 for TBI mode) Ball Number (196 MAPBGA) L8 M8 P8 N8 L9 P9 N9 P10 N10 P11 Direction Input Input Input Input Input Input Input Input Input Input I/O Type TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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Chapter 8. Package Description
8-5
MC92602 Chip Pinout Listing
Table 8-2. 196 Signal to Ball Mapping (continued)
Signal Name RECV_A_0 RECV_A_1 RECV_A_2 RECV_A_3 RECV_A_4 RECV_A_5 RECV_A_6 RECV_A_7 RECV_A_K RECV_A_9 RECV_A_IDLE RECV_A_ERR RECV_A_RCLK RLINK_A_P RLINK_A_N XLINK_A_P XLINK_A_N XMIT_B_0 XMIT_B_1 XMIT_B_2 XMIT_B_3 XMIT_B_4 XMIT_B_5 XMIT_B_6 XMIT_B_7 XMIT_B_K XMIT_B_IDLE RECV_B_0 RECV_B_1 RECV_B_2 RECV_B_3 Description Receiver A, data bit 0 Receiver A, data bit 1 Receiver A, data bit 2 Receiver A, data bit 3 Receiver A, data bit 4 Receiver A, data bit 5 Receiver A, data bit 6 Receiver A, data bit 7 Receiver A, special character (data bit 8 for TBI mode) Receiver A, data bit 9 for TBI mode Receiver A, idle detect Receiver A, error detect Receiver A, receive data clock Receiver A, positive link input Receiver A, negative link input Transmitter A, positive link out Transmitter A, negative link out Transmitter B, data bit 0 Transmitter B, data bit 1 Transmitter B, data bit 2 Transmitter B, data bit 3 Transmitter B, data bit 4 Transmitter B, data bit 5 Transmitter B, data bit 6 Transmitter B, data bit 7 Transmitter B, special character (data bit 8 for TBI mode) Transmitter B, idle enable bar, (data bit 9 for TBI mode) Receiver B, data bit 0 Receiver B, data bit 1 Receiver B, data bit 2 Receiver B, data bit 3 Ball Number (196 MAPBGA) M1 N1 M2 N2 P1 M5 M3 M4 P2 N3 L5 P4 P3 L14 M14 K12 L12 P7 N7 L7 M7 P6 N6 P5 L6 M6 N5 K3 L4 L1 J3 Direction Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Output Output Output Output I/O Type TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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MC92602 Chip Pinout Listing
Table 8-2. 196 Signal to Ball Mapping (continued)
Signal Name RECV_B_4 RECV_B_5 RECV_B_6 RECV_B_7 RECV_B_K RECV_B_9 RECV_B_IDLE RECV_B_ERR RECV_B_RCLK RLINK_B_P RLINK_B_N XLINK_B_P XLINK_B_N XMIT_C_0 XMIT_C_1 XMIT_C_2 XMIT_C_3 XMIT_C_4 XMIT_C_5 XMIT_C_6 XMIT_C_7 XMIT_C_K XMIT_C_IDLE RECV_C_0 RECV_C_1 RECV_C_2 RECV_C_3 RECV_C_4 RECV_C_5 RECV_C_6 RECV_C_7 Description Receiver B, data bit 4 Receiver B, data bit 5 Receiver B, data bit 6 Receiver B, data bit 7 Receiver B, special character (data bit 8 for TBI mode) Receiver B, data bit 9 for TBI mode Receiver B, idle detect Receiver B, error detect Receiver B, receive data clock Receiver B, positive link input Receiver B, negative link input Transmitter B, positive link out Transmitter B, negative link out Transmitter C, data bit 0 Transmitter C, data bit 1 Transmitter C, data bit 2 Transmitter C, data bit 3 Transmitter C, data bit 4 Transmitter C, data bit 5 Transmitter C, data bit 6 Transmitter C, data bit 7 Transmitter C, special character (data bit 8 for TBI mode) Transmitter C, idle enable bar, (data bit 9 for TBI mode) Receiver C, data bit 0 Receiver C, data bit 1 Receiver C, data bit 2 Receiver C, data bit 3 Receiver C, data bit 4 Receiver C, data bit 5 Receiver C, data bit 6 Receiver C, data bit 7 Ball Number (196 MAPBGA) K4 K2 K1 H3 J4 J1 G3 H2 H4 J14 H14 K11 J11 A7 B7 D7 C7 A6 B6 A5 D6 C6 B5 C1 D2 D4 E2 E3 F4 E1 F2 Direction Output Output Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output I/O Type TTL TTL TTL TTL TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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Chapter 8. Package Description
8-7
MC92602 Chip Pinout Listing
Table 8-2. 196 Signal to Ball Mapping (continued)
Signal Name RECV_C_K RECV_C_9 RECV_C_IDLE RECV_C_ERR RECV_C_RCLK RLINK_C_P RLINK_C_N XLINK_C_P XLINK_C_N XMIT_D_0 XMIT_D_1 XMIT_D_2 XMIT_D_3 XMIT_D_4 XMIT_D_5 XMIT_D_6 XMIT_D_7 XMIT_D_K XMIT_D_IDLE RECV_D_0 RECV_D_1 RECV_D_2 RECV_D_3 RECV_D_4 RECV_D_5 RECV_D_6 RECV_D_7 RECV_D_K RECV_D_9 RECV_D_IDLE Description Receiver C, special character (data bit 8 for TBI mode) Receiver C, data bit 9 for TBI mode Receiver C, idle detect Receiver C, error detect Receiver C, receive data clock Receiver C, positive link input Receiver C, negative link input Transmitter C, positive link out Transmitter C, negative link out Transmitter D, data bit 0 Transmitter D, data bit 1 Transmitter D, data bit 2 Transmitter D, data bit 3 Transmitter D, data bit 4 Transmitter D, data bit 5 Transmitter D, data bit 6 Transmitter D, data bit 7 Transmitter D, special character (data bit 8 for TBI mode) Transmitter D, idle enable bar, (data bit 9 for TBI mode) Receiver D, data bit 0 Receiver D, data bit 1 Receiver D, data bit 2 Receiver D, data bit 3 Receiver D, data bit 4 Receiver D, data bit 5 Receiver D, data bit 6 Receiver D, data bit 7 Receiver D, special character (data bit 8 for TBI mode) Receiver D, data bit 9 for TBI mode Receiver D, idle detect Ball Number (196 MAPBGA) F1 F3 G2 H1 G1 E14 F14 E11 F11 D8 C8 A8 B8 D9 A9 B9 A10 B10 E9 D3 E4 B1 C2 A1 C5 C3 C4 A2 B3 D5 Direction Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output I/O Type TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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Table 8-2. 196 Signal to Ball Mapping (continued)
Signal Name RECV_D_ERR RECV_D_RCLK RLINK_D_P RLINK_D_N XLINK_D_P XLINK_D_N TBIE HSE DDRE BSYNC_0 BSYNC_1 ADIE REPE RCCE REF_CLK MEDIA WSE WSE_GEN PLL_TPA TST_0 TST_1 LBE LBOE STNDBY RESET COREVDD Description Receiver D, error detect Receiver D, receive data clock Receiver D, positive link input Receiver D, negative link input Transmitter D, positive link out Transmitter D, negative link out 10-bit interface enable Half speed enable Double data rate enable Byte synchronization mode Select 0 Byte synchronization mode select 1 Add/Drop idle enable Repeater mode enable Recovered clock enable Reference clock Media impedance select Word synchronization enable Generate word synchronization event PLL analog test point Test mode select 0 Test mode select 1 Loop back enable Loop back output enable Standby mode enable System reset bar Core logic supply Ball Number (196 MAPBGA) A4 A3 C14 B14 E12 D12 N12 A12 D10 P12 M12 C11 A13 C12 B11 N13 B12 M10 H12 N11 L10 P13 P14 C10 A11 E5, E6, F5, G5, H5, J5, K5, K6, K7, K8, K9, K10, J10, H10, G10, F10, E10 Direction Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Input Input Input Input Vdd I/O Type TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Analog TTL TTL TTL TTL TTL TTL Supply
MOTOROLA
Chapter 8. Package Description
8-9
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Table 8-2. 196 Signal to Ball Mapping (continued)
Signal Name COREGND/PADGN D Description Core logic ground / TTL I/O ground Ball Number (196 MAPBGA) E7, E8, F6, F7, F8, F9, H6, H7, H8, H9, G6, G7, G8, G9, J6, J7, J8, J9 H13 G13 B2, D1, G4, J2, L2, L3, N4, M9, C9, B4 L13, K13, G12, E13, D11, D13, M11, M13, J13, F13, B13 K14, J12, G11, F12, D14, N14, L11, G14, A14, H11, C13 Direction GND I/O Type Ground
PLLAVDD PLLAGND PADVDD
PLL analog supply PLL analog ground TTL I/O supply
AVdd GND OVdd
Supply Ground Supply
XPADVDD
Link I/O supply
XVdd
Supply
XPADGND
Link I/O Ground
GND
Ground
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MOTOROLA
Appendix A Ordering Information
Figure A-1 provides the Motorola part numbering nomenclature for the MC92602 SERDES. For product availability, contact your local Motorola Semiconductor sales representative.
M C 9 2 6 0 2 ZT A
Product Code: XC = Pilot Production MC = Production Product Part Identifier Package: ZT = 196 pin MAPBGA Product Revision
Figure A-1. Motorola Part Number Key
MOTOROLA
Appendix A. Ordering Information
A-1
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Appendix B 8B/10B Coding Scheme
The MC92602 provides fibre channel-specific 8B/10B encoding and decoding based on the FC-1 fibre channel standard. Given 8 bits entering a channel, the 8B/10B encoding converts them to 10 bits thereby increasing the transition density of the serially transmitted signal.
B.1 Overview
The FC-1 standard applies an algorithm that ensures that no more than five 1's or 0's are transmitted consecutively, giving a transition density equal to 2.5 for each 10 bit data block. Such a density ensures proper DC balance across the link and is sufficient for good clock recovery. In the 8B/10B notation scheme, bytes are referred to as transmission characters, and each bit is represented by letters. Unencoded bits, the 8 bits that have not passed through a 8B/10B encoder, are represented by letters "A" through "H", which are bits 0 through7.
One unencoded transmission character (Byte) H Bit 7 G Bit 6 F Bit 5 E Bit 4 D Bit 3 C Bit 2 B Bit 1 A Bit 0 lsb
Figure B-1. Unencoded Transmission Character Bit Ordering
Encoded bits, those that have passed through an encoder, are represented with the letters "a" through "j", representing bits 0-9 respectively. Character (bit) ordering in the fibre channel nomenclature is little-endian, with "a" being the least significant bit in a byte.
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-1
Overview
One coded transmission character (Byte) j Bit 9 h Bit 8 g Bit 7 f Bit 6 i Bit 5 e Bit 4 d Bit 3 c Bit 2 b Bit 1 a Bit 0 lsb
Figure B-2. Encoded Transmission Character Bit Ordering
B.1.1 Naming Transmission Characters
Transmission characters are given names based on the type of data in the byte and the bit values of the character. Two types of transmission characters are specified: data and special. Data characters are labeled "D" characters and special characters are labeled "K" characters. Each transmission character has a bit value and a corresponding decimal value. These elements are combined to provide each character with a name, see Table B-1.
Table B-1. Components of a Character Name
HGF 001 1 D or K EDCBA 11100 28 8B/10B notation Data bit value Decimal value of the bit value Kind of transmission character
D28.1 = Data name assigned to this data byte if it is a data character. K28.1 = Data name assigned to this data byte if it is a special character.
B.1.2 Encoding
Following is a simplified sequence of steps in 8B/10B coding: 1. An 8-bit block of unencoded data (a transmission character) is picked up by a transmitter. 2. The transmission character is broken into sub-blocks of three bits and five bits. The letters H G and F comprise the 3-bit block, and the letters E D C B and A comprise the 5-bit block. 3. The 3-bit and 5-bit sub-blocks pass through a 3B/4B encoder and a 5B/6B encoder, respectively. A bit is added to each sub-block, such that the transmission character is encoded and expanded to a total of 10-bits. 4. At the time the character is expanded into 10 bits, it is also encoded into the proper running disparity, either positive (RD+) or negative (RD-) depending on certain calculations (see Section B.1.3, "Calculating Running Disparity"). At start-up, the transmitter assumes negative running disparity.
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Data Tables
5. The positive or negative disparity transmission character (see Figure B-3) is passed to the transmit driver, available for differentialization (See Section 2.3.3, "Transmit Driver Operation").
J H G F I E D C B A
Direction of Transmission
Figure B-3. Character Transmission
B.1.3 Calculating Running Disparity
Running disparity improves error detection and recovery. The rules for calculating the running disparity for sub-blocks are as follows (reference Fibre Channel, Gigabit Communications and I/O for Computer Networks): * Running disparity at the end of any sub-block is positive if (1) the encoded sub-block contains more 1s than 0s, (2) if the 6-bit sub-block is 6'b00 0111, or (3) if the 4-bit sub-block is 4'b0011. Running disparity at the end of any sub-block is negative if (1) the encoded sub-block contains more 0 than 1 bits, (2) if the 6-bit sub-block is 6'b11 1000, or (3) if the 4-bit sub-block is 4'b1100. Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.
*
*
B.2 Data Tables
Table B-2 displays the full valid data character 8B/10B codes. The values in the "Data Value HGFEDCBA" column are the possible bit values of the unencoded transmission characters. The current RD values are the possible positive and negative running disparity values.
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-3
Data Tables
Table B-2. Valid Data Characters
Data Name D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0 D12.0 D13.0 D14.0 D15.0 D16.0 D17.0 D18.0 D19.0 D20.0 D21.0 D22.0 D23.0 D24.0 D25.0 D26.0 D27.0 D28.0 D29.0 D30.0 D31.0 D0.2 Data Value
HGF EDCBA
Current RDabcdei fghj 100111 0100 011101 0100 101101 0100 110001 1011 110101 0100 101001 1011 011001 1011 111000 1011 111001 0100 100101 1011 010101 1011 110100 1011 001101 1011 101100 1011 011100 1011 010111 0100 011011 0100 100011 1011 010011 1011 110010 1011 001011 1011 101010 1011 011010 1011 111010 0100 110011 0100 100110 1011 010110 1011 110110 0100 001110 1011 101110 0100 011110 0100 101011 0100 100111 0101
Current RD+ abcdei fghj 011000 1011 100010 1011 010010 1011 110001 0100 001010 1011 101001 0100 011001 0100 000111 0100 000110 1011 100101 0100 010101 0100 110100 0100 001101 0100 101100 0100 011100 0100 101000 1011 100100 1011 100011 0100 010011 0100 110010 0100 001011 0100 101010 0100 011010 0100 000101 1011 001100 1011 100110 0100 010110 0100 001001 1011 001110 0100 010001 1011 100001 1011 010100 1011 011000 0101
Data Name D0.1 D1.1 D2.1 D3.1 D4.1 D5.1 D6.1 D7.1 D8.1 D9.1 D10.1 D11.1 D12.1 D13.1 D14.1 D15.1 D16.1 D17.1 D18.1 D19.1 D20.1 D21.1 D22.1 D23.1 D24.1 D25.1 D26.1 D27.1 D28.1 D29.1 D30.1 D31.1 D0.3
Data Value
HGF EDCBA
Current RDabcdei fghj 100111 1001 011101 1001 101101 1001 110001 1001 110101 1001 101001 1001 011001 1001 111000 1001 111001 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 010111 1001 011011 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 111010 1001 110011 1001 100110 1001 010110 1001 110110 1001 001110 1001 101110 1001 011110 1001 101011 1001 100111 0011
Current RD+ abcdei fghj 011000 1001 100010 1001 010010 1001 110001 1001 001010 1001 101001 1001 011001 1001 000111 1001 000110 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 101000 1001 100100 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 000101 1001 001100 1001 100110 1001 010110 1001 001001 1001 001110 1001 010001 1001 100001 1001 010100 1001 011000 1100
000 00000 000 00001 000 00010 000 00011 000 00100 000 00101 000 00110 000 00111 000 01000 000 01001 000 01010 000 01011 000 01100 000 01101 000 01110 000 01111 000 10000 000 10001 000 10010 000 10011 000 10100 000 10101 000 10110 000 10111 000 11000 000 11001 000 11010 000 11011 000 11100 000 11101 000 11110 000 11111 010 00000
001 00000 001 00001 001 00010 001 00011 001 00100 001 00101 001 00110 001 00111 001 01000 001 01001 001 01010 001 01011 001 01100 001 01101 001 01110 001 01111 001 10000 001 10001 001 10010 001 10011 001 10100 001 10101 001 10110 001 10111 001 11000 001 11001 001 11010 001 11011 001 11100 001 11101 001 11110 001 11111 011 00000
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Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D1.2 D2.2 D3.2 D4.2 D5.2 D6.2 D7.2 D8.2 D9.2 D10.2 D11.2 D12.2 D13.2 D14.2 D15.2 D16.2 D17.2 D18.2 D19.2 D20.2 D21.2 D22.2 D23.2 D24.2 D25.2 D26.2 D27.2 D28.2 D29.2 D30.2 D31.2 D0.4 D1.4 Data Value
HGF EDCBA
Current RDabcdei fghj 011101 0101 101101 0101 110001 0101 110101 0101 101001 0101 011001 0101 111000 0101 111001 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 010111 0101 011011 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 111010 0101 110011 0101 100110 0101 010110 0101 110110 0101 001110 0101 101110 0101 011110 0101 101011 0101 100111 0010 011101 0010
Current RD+ abcdei fghj 100010 0101 010010 0101 110001 0101 001010 0101 101001 0101 011001 0101 000111 0101 000110 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 101000 0101 100100 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 000101 0101 001100 0101 100110 0101 010110 0101 001001 0101 001110 0101 010001 0101 100001 0101 010100 0101 011000 1101 100010 1101
Data Name D1.3 D2.3 D3.3 D4.3 D5.3 D6.3 D7.3 D8.3 D9.3 D10.3 D11.3 D12.3 D13.3 D14.3 D15.3 D16.3 D17.3 D18.3 D19.3 D20.3 D21.3 D22.3 D23.3 D24.3 D25.3 D26.3 D27.3 D28.3 D29.3 D30.3 D31.3 D0.5 D1.5
Data Value
HGF EDCBA
Current RDabcdei fghj 011101 0011 101101 0011 110001 1100 110101 0011 101001 1100 011001 1100 111000 1100 111001 0011 100101 1100 010101 1100 110100 1100 001101 1100 101100 1100 011100 1100 010111 0011 011011 0011 100011 1100 010011 1100 110010 1100 001011 1100 101010 1100 011010 1100 111010 0011 110011 0011 100110 1100 010110 1100 110110 0011 001110 1100 101110 0011 011110 0011 101011 0011 100111 1010 011101 1010
Current RD+ abcdei fghj 100010 1100 010010 1100 110001 0011 001010 1100 101001 0011 011001 0011 000111 0011 000110 1100 100101 0011 010101 0011 110100 0011 001101 0011 101100 0011 011100 0011 101000 1100 100100 1100 100011 0011 010011 0011 110010 0011 001011 0011 101010 0011 011010 0011 000101 1100 001100 1100 100110 0011 010110 0011 001001 1100 001110 0011 010001 1100 100001 1100 010100 1100 011000 1010 100010 1010
010 00001 010 00010 010 00011 010 00100 010 00101 010 00110 010 00111 010 01000 010 01001 010 01010 010 01011 010 01100 010 01101 010 01110 010 01111 010 10000 010 10001 010 10010 010 10011 010 10100 010 10101 010 10110 010 10111 010 11000 010 11001 010 11010 010 11011 010 11100 010 11101 010 11110 010 11111 100 00000 100 00001
011 00001 011 00010 011 00011 011 00100 011 00101 011 00110 011 00111 011 01000 011 01001 011 01010 011 01011 011 01100 011 01101 011 01110 011 01111 011 10000 011 10001 011 10010 011 10011 011 10100 011 10101 011 10110 011 10111 011 11000 011 11001 011 11010 011 11011 011 11100 011 11101 011 11110 011 11111 101 00000 101 00001
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-5
Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D2.4 D3.4 D4.4 D5.4 D6.4 D7.4 D8.4 D9.4 D10.4 D11.4 D12.4 D13.4 D14.4 D15.4 D16.4 D17.4 D18.4 D19.4 D20.4 D21.4 D22.4 D23.4 D24.4 D25.4 D26.4 D27.4 D28.4 D29.4 D30.4 D31.4 D0.6 D1.6 D2.6 Data Value
HGF EDCBA
Current RDabcdei fghj 101101 0010 110001 1101 110101 0010 101001 1101 011001 1101 111000 1101 111001 0010 100101 1101 010101 1101 110100 1101 001101 1101 101100 1101 011100 1101 010111 0010 011011 0010 100011 1101 010011 1101 110010 1101 001011 1101 101010 1101 011010 1101 111010 0010 110011 0010 100110 1101 010110 1101 110110 0010 001110 1101 101110 0010 011110 0010 101011 0010 100111 0110 011101 0110 101101 0110
Current RD+ abcdei fghj 010010 1101 110001 0010 001010 1101 101001 0010 011001 0010 000111 0010 000110 1101 100101 0010 010101 0010 110100 0010 001101 0010 101100 0010 011100 0010 101000 1101 100100 1101 100011 0010 010011 0010 110010 0010 001011 0010 101010 0010 011010 0010 000101 1101 001100 1101 100110 0010 010110 0010 001001 1101 001110 0010 010001 1101 100001 1101 010100 1101 011000 0110 100010 0110 010010 0110
Data Name D2.5 D3.5 D4.5 D5.5 D6.5 D7.5 D8.5 D9.5 D10.5 D11.5 D12.5 D13.5 D14.5 D15.5 D16.5 D17.5 D18.5 D19.5 D20.5 D21.5 D22.5 D23.5 D24.5 D25.5 D26.5 D27.5 D28.5 D29.5 D30.5 D31.5 D0.7 D1.7 D2.7
Data Value
HGF EDCBA
Current RDabcdei fghj 101101 1010 110001 1010 110101 1010 101001 1010 011001 1010 111000 1010 111001 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 010111 1010 011011 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 010101 1010 111010 1010 110011 1010 100110 1010 010110 1010 110110 1010 001110 1010 101110 1010 011110 1010 101011 1010 100111 0001 011101 0001 101101 0001
Current RD+ abcdei fghj 010010 1010 110001 1010 001010 1010 101001 1010 011001 1010 000111 1010 000110 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 101000 1010 100100 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 011010 1010 000101 1010 001100 1010 100110 1010 010110 1010 001001 1010 001110 1010 010001 1010 100001 1010 010100 1010 011000 1110 100010 1110 010010 1110
100 00010 100 00011 100 00100 100 00101 100 00110 100 00111 100 01000 100 01001 100 01010 100 01011 100 01100 100 01101 100 01110 100 01111 100 10000 100 10001 100 10010 100 10011 100 10100 100 10101 100 10110 100 10111 100 11000 100 11001 100 11010 100 11011 100 11100 100 11101 100 11110 100 11111 110 00000 110 00001 110 00010
101 00010 101 00011 101 00100 101 00101 101 00110 101 00111 101 01000 101 01001 101 01010 101 01011 101 01100 101 01101 101 01110 101 01111 101 10000 101 10001 101 10010 101 10011 101 10100 101 10101 101 10110 101 10111 101 11000 101 11001 101 11010 101 11011 101 11100 101 11101 101 11110 101 11111 111 00000 111 00001 111 00010
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Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6 D27.6 D28.6 D29.6 D30.6 D31.6 Data Value
HGF EDCBA
Current RDabcdei fghj 110001 0110 110101 0110 101001 0110 011001 0110 111000 0110 111001 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 010111 0110 011011 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 111010 0110 110011 0110 100110 0110 010110 0110 110110 0110 001110 0110 101110 0110 011110 0110 101011 0110
Current RD+ abcdei fghj 110001 0110 001010 0110 101001 0110 011001 0110 000111 0110 000110 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 101000 0110 100100 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 000101 0110 001100 0110 100110 0110 010110 0110 001001 0110 001110 0110 010001 0110 100001 0110 010100 0110
Data Name D3.7 D4.7 D5.7 D6.7 D7.7 D8.7 D9.7 D10.7 D11.7 D12.7 D13.7 D14.7 D15.7 D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.7 D30.7 D31.7
Data Value
HGF EDCBA
Current RDabcdei fghj 110001 1110 110101 0001 101001 1110 011001 1110 111000 1110 111001 0001 100101 1110 010101 1110 110100 1110 001101 1110 101100 1110 011100 1110 010111 0001 011011 0001 100011 0111 010011 0111 110010 1110 001011 0111 101010 1110 011010 1110 111010 0001 110011 0001 100110 1110 010110 1110 110110 0001 001110 1110 101110 0001 011110 0001 101011 0001
Current RD+ abcdei fghj 110001 0001 001010 1110 101001 0001 011001 0001 000111 0001 000110 1110 100101 0001 010101 0001 110100 1000 001101 0001 101100 1000 011100 1000 101000 1110 100100 1110 100011 0001 010011 0001 110010 0001 001011 0001 101010 0001 011010 0001 000101 1110 001100 1110 100110 0001 010110 0001 001001 1110 001110 0001 010001 1110 100001 1110 010100 1110
110 00011 110 00100 110 00101 110 00110 110 00111 110 01000 110 01001 110 01010 110 01011 110 01100 110 01101 110 01110 110 01111 110 10000 110 10001 110 10010 110 10011 110 10100 110 10101 110 10110 110 10111 110 11000 110 11001 110 11010 110 11011 110 11100 110 11101 110 11110 110 11111
111 00011 111 00100 111 00101 111 00110 111 00111 111 01000 111 01001 111 01010 111 01011 111 01100 111 01101 111 01110 111 01111 111 10000 111 10001 111 10010 111 10011 111 10100 111 10101 111 10110 111 10111 111 11000 111 11001 111 11010 111 11011 111 11100 111 11101 111 11110 111 11111
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-7
Data Tables
Table B-3 displays the full valid special character 8B/10B codes.
Table B-3. Valid Special Characters
Name K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 Data Value
HGF EDCBA
Current RDabcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010
Current RD+ abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101
Name K28.6 K28.7 K23.7 K27.7 K29.7 K30.7
Data Value
HGF EDCBA
Current RDabcdei fghj 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000
Current RD+ abcdie fghj 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111
000 11100 001 11100 010 11100 011 11100 100 11100 101 11100
110 11100 111 11100 111 10111 111 11011 111 11101 111 11110
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Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and definitions included in the glossary are reprinted from IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright (c)1985 by the Institute of Electrical and Electronics Engineers, Inc., with the permission of the IEEE.
A B
Asserted. Indicates active state of signal has been set. Refers to either inputs or outputs. BERC. Bit Error Rate Checking. BERT. Bit Error Rate Testing. BIST. Built-In Self-Test. Bit alignment. Refers to the transition tracking loop recovering data bits from the serial input stream. Byte. Eight bits of uncoded data. Byte alignment. Receiver identification of character boundaries through use of Idle character recognition.
C G
Character. An 8B/10B encoded byte of data. Gigabit. A unit of speed of data transfer. One gigabit indicates a data throughput of 1 billion bits per second requiring a transfer rate of 1.25 billion symbols per second of 8B/10B encoded data. Gigabaud. A unit of speed of symbol transfer. One gigabaud indicates a data throughput of 800 million bits per second requiring a transfer rate of 1.0 billion symbols per second of 8B/10B encoded data.
I
ISI. Inter Symbol Interference, a distortion caused by the high-frequency loss characteristics of the transmission media.
MOTOROLA
Glossary
Glossary-1
N P R
Negated. Indicates inactive state of signal has been set. Refers to either inputs or outputs. PLL. Phase Locked Loop. PPM. parts per million. Running disparity. The amount of DC imbalance over a history of symbols transmitted over a link. Equal to the difference between the number of one and zero symbols transmitted. Symbol. One piece of information sent across the link; different from a bit in that bit implies data where symbol is encoded data. Word synchronization. Alignment of four or more receivers' data by adjusting for differences in media and systemic delay between them such that data is presented by the receivers in the same grouping as they were transmit.
S W
Glossary-2
MC92602 SERDES Reference Manual
MOTOROLA
Index
Numerics
8B/10B coding scheme, B-1 decoder, 3-9 encoder operation, 2-6 encoding sequence of, B-2 notation, B-1 Specifications, 7-1
F
Features, 1-2 Frequency offset, 3-8 Functional description, 2-4
G
General Parameters, 7-1
A
Absolute Maximum Ratings, 7-2 AC Electrical Characteristics, 7-4 Alignment loss, 3-6
H
Half-Speed Mode, 3-14 HSTL reference voltage recommendation, 5-5
B
BIST Error Codes, 6-4 Boundary-Scan Register, 6-3 Byte alignment, 3-6 Interface, 3-11 interface, 3-10 Byte interface mode, 3-10
I
IEEE Std. 1149.1 Implementation, 6-1 Input Amplifier, 3-5 Instruction Register, 6-2 Instructions, 6-2
J
JTAG I/O Timing Diagram, 7-9 I/O Timing Specification, 7-9
C
Configuration and Control Signals, 5-2 Conventions, xv COREGND/PADGND, 8-10 COREVDD, 8-9
L
Link Differential Input Timing Diagram, 7-8 Input Timing Specification, 7-8 Output Specification, 7-8 Output Timing Diagram, 7-8 Loop, 6-6 Loop-Back BIST Sequence System Test Mode, 6-6 Loop-Back Test Mode, 2-7
D
Data Recovery, 3-5 DC Electrical Specifications, 7-3 Device Identification Register, 6-3 Disparity calculating, B-3
M E
Electrical Characteristics, 7-1 MC92602 Block Diagram, 1-3 Overview, 1-1
MOTOROLA
Index
Index-1
Receiver Block Diagram, 3-2 Modes Half-Speed Mode, 3-14 Recovered Clock Timing Mode, 3-12 Reference Clock Timing Mode, 3-13 Repeater Mode, 3-14
S
Startup, 4-2, 5-2
T
TAP Interface Signals, 6-1 Ten-Bit Interface, 3-10 Ten-bit Interface, 3-11 Test Access Port Interface Signals, 6-1 Test modes Loop-back BIST Sequence System Test Mode, 6-6 Transition density, B-1 Transition Tracking Loop, 3-5 Transition Tracking Loop and Data Recovery, 3-5 Transmission characters naming, types, B-2 overview, B-1 Transmit Data Input Register Operation, 2-4 Transmit Driver Operation, 2-6 Transmit Interface Clock Configuration, 2-6 Transmitter, 2-1 DDR Interface Timing, 7-4 DDR Timing Specification, 7-5 Transmitter Block Diagram, 2-2 Transmitter Control States, 2-5 Transmitting, 2-5 Transmitting Pre-Coded Data, 2-5 Transmitting Uncoded Data, 2-5
O
Operating Conditions, 7-2
P
Package Description, 8-1 Nomenclature and Dimensions, 8-1 Parameter Summary, 8-1 Pinout Listing, 8-5 Thermal characteristics, 8-5 PADVDD, 8-10 Performance, 6-3 Phase Locked Loop (PLL) Power Supply Filtering, 5-4 Pinout listing, 8-5 PLL_TPA, 8-9 PLLAGND, 8-10 PLLAVDD, 8-10 Power supply decoupling recommendations, 5-4 requirements, 5-3 Proper running disparity, B-2
U R
Receiver, 3-1 Block Diagram, 3-2 DDR Timing Specification, 7-5 Functional Description, 3-4 interface, 3-9 Interface DDR Timing Diagram, 7-5 Interface Error Codes, 3-10, 3-11 Interface Signals, 3-2, 3-3 Recovered Clock Specification, 7-7 Timing Diagram, 7-7 Timing Mode, 3-12 Reference Clock Specification, 7-6 Timing Diagram, 7-6 Reference Clock Timing Mode, 3-13 References, 1-5 Repeater Mode, 2-8, 3-14 RESET_B, 8-9 Revision History, 1-5 Uncoded data in 8B/10B coding scheme, B-1
V
Voltage reference for single-ended reference clock use, 5-5 Voltage Reference for Single-Ended Reference Clock Use, 5-5
W
Word Synchronization Mode, 4-5 States, 3-8
X
XMIT_A_IDLE_B, 8-5 XMIT_B_IDLE_B, 8-6 XMIT_C_IDLE_B, 8-7 XMIT_D_IDLE_B, 8-8 XPADGND, 8-10 XPADVDD, 8-10
Index-2
MC92602 SERDES Reference Manual
MOTOROLA
Introduction
Transmitter Receiver Rate Adaption of IEEE Standard 802.3 Packet Streams System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
1 2 3 4 5 6 7 8 A B IND GLO IND
1 1 2 3 4 5 6 7 8 A B GLO IND
Introduction
Transmitter Receiver Rate Adaption of IEEE Standard 802.3 Packet Streams System Design Considerations Test Features Electrical Specifications and Characteristics Package Description Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index

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